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TLP705A Scheda tecnica(PDF) 2 Page - Toshiba Semiconductor |
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TLP705A Scheda tecnica(HTML) 2 Page - Toshiba Semiconductor |
2 / 16 page TLP705A 2 4. 4. 4. 4. Packaging and Pin Configuration Packaging and Pin Configuration Packaging and Pin Configuration Packaging and Pin Configuration 11-5J1S 1: Anode 2: N.C. 3: Cathode 4: GND 5: VO (Output) 6: VCC 5. 5. 5. 5. Internal Circuit (Note) Internal Circuit (Note) Internal Circuit (Note) Internal Circuit (Note) Note: A 0.1-µF bypass capacitor must be connected between pin 6 and pin 4. 6. 6. 6. 6. Principle of Operation Principle of Operation Principle of Operation Principle of Operation 6.1. 6.1. 6.1. 6.1. Truth Table Truth Table Truth Table Truth Table Input H L LED ON OFF M1 ON OFF M2 OFF ON Output H L 6.2. 6.2. 6.2. 6.2. Mechanical Parameters Mechanical Parameters Mechanical Parameters Mechanical Parameters Characteristics Creepage distances Clearance distances Internal isolation thickness 7.62-mm Pitch TLP705A 7.0 (min) 7.0 (min) 0.4 (min) 10.16-mm Pitch TLP705AF 8.0 (min) 8.0 (min) 0.4 (min) Unit mm 2015-12-25 Rev.5.0 ©2015 Toshiba Corporation |
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