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UC1875-SP Scheda tecnica(PDF) 4 Page - Texas Instruments

Il numero della parte UC1875-SP
Spiegazioni elettronici  Rad-Tolerant Class-V, Phase Shift Resonant Controller
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UC1875-SP
SLUSAQ9B – DECEMBER 2011 – REVISED DECEMBER 2015
www.ti.com
Pin Functions
PIN
I/O
DESCRIPTION
NAME
CDIP
LCCC
CFP
Bi-directional clock and synchronization pin. Used as an output, this
CLOCK/
17
9
20
I/O
pin provides a clock signal. As an input, this pin provides a
SYNC
synchronization point.
The positive input to the current-fault comparator whose reference is
set internally to fixed 2.5 V (separate from VREF). When the voltage at
this pin exceeds 2.5 V, the current-fault latch is set, the outputs are
forced off and a SOFT START cycle is initiated. If a constant voltage
C/S+
5
22
6
I
above 2.5 V is applied to this pin the outputs are disabled from
switching and held in a low state until the C/S (+) pin is brought below
2.5 V. The outputs may begin switching at 0 degrees phase shift
before the SOFT START pin begins to rise, this condition will not
prematurely deliver power to the load.
Output delay control. The users programmed current flowing from
these pins to GND set the turn-on delay for the corresponding output
pair. This delay is introduced between turn-off of one switch and turn-
DELAY
15
7
18
O
on of another in the same leg of the bridge to provide a dead time in
SET A/B
which the resonant switching of the external power switches takes
place. Separate delays are provided for the two half bridges to
accommodate differences in the resonant capacitor charging currents.
Output delay control. The users programmed current flowing from
these pins to GND set the turn-on delay for the corresponding output
pair. This delay is introduced between turn-off of one switch and turn-
DELAY
7
24
8
O
on of another in the same leg of the bridge to provide a dead time in
SET C/D
which the resonant switching of the external power switches takes
place. Separate delays are provided for the two half bridges to
accommodate differences in the resonant capacitor charging currents.
This pin is normally connected to a reference voltage used for
E/A+
4
21
5
I
comparison with the sensed power supply output voltage level at the
E/A(-) pin.
This pin is normally connected to the voltage divider resistors which
E/A–
3
20
4
I
sense the power supply output level.
Error amplifier output. This is the gain stage for overall feedback
control. Error amplifier output voltage levels below 1 volt will force 0°
E/A OUT
2
17
3
O
phase shift. Since the error amplifier has a relatively low current drive
(COMP)
capability, the output may be overridden by driving with a sufficiently
low impedance source.
Oscillator frequency set pin. A resistor and a capacitor from FREQ
FREQ
16
8
19
O
SET to GND will set oscillator frequency according to the following
SET
relationship: f = 4/(RfSET × CRAMP).
Signal ground. All voltages are measured with respect to ground
(GND). The timing capacitor, on the FREQ SET pin, and bypass
GND
20
14
23
_
capacitor on the VREF pin, bypass capacitors on VIN and the ramp
capacitor, on the RAMP pin, should be connected directly to the
ground plane near the signal ground pin.
5, 6, 12, 13,
N/C
15, 18, 19,
1, 12, 13, 24
_
No connection.
25
The outputs are 2 A totem-pole drivers optimized for both MOSFET
gates and level shifting transformers. The outputs operate as pair with
a nominal 50% duty cycle. The A-B pair is intended to drive one half
OUT A
14
4
17
O
bridge in the external power stage and is synchronized with the clock
waveform. The C-D pair will drive the other half-bridge with switching
phase shifted with respect to the A-B outputs.
OUT B
13
3
16
O
See OUT A description.
OUT C
9
27
10
O
See OUT A description.
OUT D
8
26
9
O
See OUT A description.
Power ground. VC should be bypassed with a ceramic capacitor from
the VC pin to the section of the ground plane that is connected to
POWER
12
2
15
_
PWR GND. Any required bulk reservoir capacitor should parallel this
GND
one. Power ground and signal ground may be joined at a signal point
to optimize noise rejection and minimize DC drops.
4
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Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: UC1875-SP


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