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54LS163AE Scheda tecnica(PDF) 6 Page - National Semiconductor (TI) |
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54LS163AE Scheda tecnica(HTML) 6 Page - National Semiconductor (TI) |
6 / 12 page ’LS163 Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) (Continued) From (Input) RL e 2kX Symbol Parameter To (Output) CL e 15 pF CL e 50 pF Units Min Max Min Max tPLH Propagation Delay Time Clock to Any Q 24 30 ns Low to High Level Output (Load Low) tPHL Propagation Delay Time Clock to Any Q 27 38 ns High to Low Level Output (Load Low) tPLH Propagation Delay Time Enable T to 14 27 ns Low to High Level Output Ripple Carry tPHL Propagation Delay Time Enable T to 15 27 ns High to Low Level Output Ripple Carry tPHL Propagation Delay Time Clear to Any Q 28 45 ns High to Low Level Output (Note 1) Note 1 The propagation delay clear to output is measured from the clock input transition Logic Diagram LS163A TLF6397 – 2 The LS161A is similar however the clear buffer is connected directly to the flip flops 6 |
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