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AD6679-500EBZ Scheda tecnica(PDF) 4 Page - Analog Devices |
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AD6679-500EBZ Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 81 page AD6679 Data Sheet Rev. B | Page 4 of 81 The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO) and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes, selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6679 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) pass unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications and supports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6679 between the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles. In addition to the DDC blocks, the AD6679 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly reduce the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD6679 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal that the ADC digitized. The output data is routed directly to the one external 14-bit LVDS output port, supporting double data rate (DDR) formatting. An external data clock and a clock status bit are offered for data capture flexibility. The AD6679 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V capable 3-wire SPI. The AD6679 is available in a Pb-free, 196-ball BGA_ED, and is specified over the −40°C to +85°C industrial temperature range. PRODUCT HIGHLIGHTS 1. Wide full power bandwidth IF sampling of signals up to 2 GHz. 2. Buffered inputs with programmable input termination eases filter design and implementation. 3. Four integrated wideband decimation filters and NCO blocks support multiband receivers. 4. Flexible SPI controls various product features and functions to meet specific system requirements. 5. Programmable fast overrange detection and signal monitoring. 6. Programmable fast overrange detection. 7. 12 mm × 12 mm, 196-ball BGA_ED. |
Codice articolo simile - AD6679-500EBZ |
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Descrizione simile - AD6679-500EBZ |
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