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AD6676 Scheda tecnica(PDF) 2 Page - Analog Devices |
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AD6676 Scheda tecnica(HTML) 2 Page - Analog Devices |
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2 / 90 page  AD6676 Data Sheet Rev. A | Page 2 of 90 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Product Highlights ........................................................................... 4 Specifications..................................................................................... 5 Digital High Speed SERDES Specifications.............................. 7 CLK± to SYSREF± Timing Diagram......................................... 8 Digital CMOS Input/Output Specifications ............................. 8 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Nominal Performance for IF = 115 MHz (Direct Sampling VHF Receiver) ............................................................................ 12 Nominal Performance for IF = 140 MHz (µW Point-to-Point Receivers)..................................................................................... 14 Nominal Performance for IF = 181 MHz (Wireless Infrastructure Receiver)............................................................. 15 Nominal Performance for IF = 250 MHz AND BW = 75 MHz ....................................................................................................... 17 Nominal Performance for IF = 350 MHz AND BW = 160 MHz ...................................................................................... 19 Equivalent Circuits......................................................................... 21 Terminology .................................................................................... 22 Theory of Operation ...................................................................... 23 Overview...................................................................................... 23 Band-Pass Σ-Δ ADC Architecture........................................... 24 Σ-Δ ADC Configuration Considerations................................ 28 Attenuator.................................................................................... 33 Clock Synthesizer ....................................................................... 35 Digital Processing Blocks .............................................................. 38 Digital Signal Processing Path.................................................. 39 AGC Features and Peak Detection........................................... 42 GPIO Functionality.................................................................... 44 Power Saving Modes .................................................................. 44 Introduction to the JESD204B Interface ................................. 45 Functional Overview ................................................................. 47 JESD204B Link Establishment ................................................. 47 Physical Layer Input/Outputs................................................... 49 Configuring the JESD204B Link.............................................. 50 Synchronization Using SYSREF±............................................. 51 Applications Information .............................................................. 53 Analog Input Considerations ................................................... 53 Clock Input Considerations...................................................... 54 IF Frequency Planning .............................................................. 56 PCB Design Guidelines ............................................................. 57 Powering the AD6676................................................................ 59 AD6676 Start-Up Initialization................................................ 61 Serial Port Interface (SPI).............................................................. 64 SPI Register Map Description .................................................. 64 SPI Operation ............................................................................. 64 Register Memory Map and Details .............................................. 66 Register Memory Map............................................................... 66 Register Details........................................................................... 68 Outline Dimensions....................................................................... 90 Ordering Guide .......................................................................... 90 |
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