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54F827LM Scheda tecnica(PDF) 3 Page - National Semiconductor (TI) |
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54F827LM Scheda tecnica(HTML) 3 Page - National Semiconductor (TI) |
3 / 8 page Unit LoadingFan Out 54F74F Pin Names Description UL Input IIH IIL HIGHLOW Output IOH IOL OE1 OE2 Output Enable Input 1010 20 mA b06 mA D0–D7 Data Inputs 1010 20 mA b06 mA O0–O7 Data Outputs TRI-STATE 6001066 (80) b12 mA64 mA (48 mA) Functional Description The ’F827 and ’F828 are line drivers designed to be em- ployed as memory address drivers clock drivers and bus- oriented transmittersreceivers which provide improved PC board density The devices have TRI-STATE outputs con- trolled by the Output Enable (OE) pins The outputs can sink 64 mA (48 mA mil) and source 15 mA Input clamp diodes limit high-speed termination effects Function Table Inputs Outputs OE Dn On Function ’F827 ’F828 L H H L Transparent L L L H Transparent H X Z Z High Z H e HIGH Voltage level L e LOW Voltage Level Z e High Impedance X e Immaterial Logic Diagrams ’F827 TLF9598 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays ’F828 TLF9598 – 11 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 3 |
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