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FM1608-120-P Scheda tecnica(PDF) 4 Page - Ramtron International Corporation |
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FM1608-120-P Scheda tecnica(HTML) 4 Page - Ramtron International Corporation |
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4 / 12 page  Ramtron FM1608 28 July 2000 4/12 cycle. Therefore, any operation including read or write can occur immediately following a write. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Pre-charge Operation The pre-charge operation is an internal condition where the state of the memory is prepared for a new access. All memory cycles consist of a memory access and a pre -charge. The pre-charge is user initiated by taking the /CE signal high or inactive. It must remain high for at least the minimum pre-charge timing specification. The user dictates the beginning of this operation since a pre-charge will not begin until /CE rises. However the device has a maximum /CE low time specification that must be satisfied. Endurance and Memory Architecture Data retention is specified in the electrical specifications below. This section elaborates on the relationship between data retention and endurance. FRAM offers substantially higher write endurance than other nonvolatile memories. Above a certain level, however, the effect of increasing memory accesses on FRAM produces an increase in the soft error rate. There is a higher likelihood of data loss but the memory continues to function properly. This effect becomes significant only after 100 million (1E8) read/write cycles, far more than allowed by other nonvolatile memory technologies. Endurance is a soft specification. Therefore, the user may operate the device with different levels of cycling for different portions of the memory. For example, critical data needing the highest reliability level could be stored in memory locations that receive comparatively few cycles. Data with frequent changes or shorter-term use could be located in an area receiving many more cycles. A scratchpad area, needing little if any retention can be cycled virtually without limit. Internally, a FRAM operates with a read and restore mechanism similar to a DRAM. Therefore, each cycle, be it read or write, involves a change of state. The memory architecture is based on an array of rows and columns. Each access causes an endurance cycle for an entire row. Therefore, data locations targeted for substantially differing numbers of cycles should not be located within the same row. To balance the endurance cycles and allow the user the maximum flexibility, the FM1608 employs a unique memory organization as described below. The memory array is divided into 8 blocks, each 1Kx8. The 3-upper address lines decode the block selection as shown in Figure 2. Data targeted for significantly different numbers of cycles should be located in separate blocks since memory rows do not extend across block boundaries. Figure 2. Address Blocks Each block of 1Kx8 consists of 256 rows and 4 columns. The address lines A0-A7 decode row selection and A8-A9 lines decode column selection. This scheme facilitates a relatively uniform distribution of cycles across the rows of a block. By allowing the address LSBs to decode row selection, the user avoids applying multiple cycles to the same row when accessing sequential data. For example, 256 bytes can be accessed sequentially without accessing the same row twice. In this example, one cycle would be applied to each row. An entire block of 1Kx8 can be read or written with only four cycles applied to each row. Figure 3 illustrates the organization within a memory block. |
Codice articolo simile - FM1608-120-P |
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