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TS80000 Scheda tecnica(PDF) 11 Page - Semtech Corporation

Il numero della parte TS80000
Spiegazioni elettronici  High Efficiency Transmitter Controller for Wireless Power Systems
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Produttore elettronici  SEMTECH [Semtech Corporation]
Homepage  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

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TS80000
Final Datasheet
Rev 1.4
March 19, 2015
www.semtech.com
11 of 37
Semtech
Proprietary & Confidential
Status0 Register (STATUS0)
Address:
0x08
Reset value:
0xC0
Bit 7
CTS: Clear To Send
This bit indicates if a new read/write register access can be issued to the controller. This bit
is not reset by hardware when read.
0: The controller is busy processing a previous register access. New commands should not
be sent to the controller.
1: The controller can accept a new register access command over the communication
interface.
Bit 6
CTS_API: Clear to Send for API
This bit indicates if a new API call or API read request can be issued to the controller. This
bit is not reset by hardware when read.
0: The controller is busy processing a previous API call. New API calls should not be sent to
the controller.
1: The controller can accept a new API call over the communication interface.
Bit 5
CTS_IF: Clear To Send Event Interrupt Flag
0: No event is signaled for the CTS bit or the corresponding bit in the INTERRUPT_MASK0
register is cleared.
1: The CTS bit has been set and the corresponding bit in the INTERRUPT_MASK0 register is
set. Reset to 0 by hardware when the STATUS0 register is read.
Bit 4
CTS_API_IF: Clear to Send for API Event Interrupt Flag
0: No event is signaled for the CTS_API bit.
1: The CTS_API bit has been set and the corresponding bit in the INTERRUPT_MASK0
register is set. Reset to 0 by hardware when the STATUS0 register is read.
Bit 3
STATUS3_IF: STATUS1 Event Interrupt Flag
0: No event is signaled in the STATUS3 register or the corresponding bit in the INTERRUPT_
MASK0 register is cleared.
1: An event is signaled in the STATUS3 register and the corresponding bit in the
INTERRUPT_MASK3 register is set. Reset to 0 by hardware when the STATUS3 register is read.
Bit 2
STATUS2_IF: STATUS2 Event Interrupt Flag
0: No event is signaled in the STATUS2 register or the corresponding bit in the INTERRUPT_
MASK0 register is cleared.
1: An event is signaled in the STATUS2 register and the corresponding bit in the
INTERRUPT_MASK2 register is set. Reset to 0 by hardware when the STATUS2 register is read.
Bit 1
STATUS1_IF: STATUS1 Event Interrupt Flag
0: No event is signaled in the STATUS1 register or the corresponding bit in the INTERRUPT_
MASK0 register is cleared.
1: An event is signaled in the STATUS1 register and the corresponding bit in the
INTERRUPT_MASK1 register is set. Reset to 0 by hardware when the STATUS1 register is read.
Bit 0
Reserved


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