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GS6081-INTE3 Scheda tecnica(PDF) 8 Page - Semtech Corporation |
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GS6081-INTE3 Scheda tecnica(HTML) 8 Page - Semtech Corporation |
8 / 19 page GS6081 Final Data Sheet Rev.4 PDS-060046 July 2014 8 of 19 Proprietary & Confidential www.semtech.com Rise/Fall time tr, tf 5.94Gb/s — 66 — ps 3, 8 tr, tf SD_EN=0 — — 135 ps 3 tr, tf SD_EN=1 400 — 800 ps 3 Mismatch in rise/fall time tr, tf HD/3G/UHD modes — — 35 ps 8 Duty cycle distortion — SD_EN=0, 5.94Gb/s — 18 — ps 4, 5, 8 — SD_EN=0, 2.97Gb/s — — 14 ps 4, 5 — SD_EN=0, 1.485Gb/s — — 20 ps 4, 5 —SD_EN=1 — — 50 ps 4, 5 Overshoot — SD_EN=0, — — 10 % 4 Output Return Loss ORL 5 MHz – 1.485GHz 16 19 — dB 6 1.485GHz – 2.97GHz 12 15 — dB 6 Output Voltage Swing VOUT RSET = 750Ω 750 800 850 mVpp 4 Input Voltage Swing VDDI Guaranteed functional. 100 — 2200 mVppd — Guaranteed to meet all published specifications. 250 2200 mVppd — Output Disable Delay — Any output enabled to all outputs disabled —— 80 ns — Output Enable Delay — All outputs disabled to any output enabled. —— 4 μs— — One output enabled to both outputs enabled. —— 500 ns 7 Notes: 1. The input coupling capacitor must be set accordingly for lower data rates. 2. Turning on input trace equalization will reduce jitter in most applications. 3. Rise/Fall time measured between 20% and 80% applies to 800mVpp output swing only. 4. Single-ended into a 75 Ω external load. 5. Calculated as the actual positive bit-width compared to the expected positive bit-width using a 1010 pattern. 6. ORL depends on board design. The GS6081 achieves this specification on Semtech's evaluation boards. 7. This Output Enable Delay applies only to the newly enabled output. The output that is already enabled is not impacted in this case. 8. Results based on Validation Data using recommended Application Circuit. Table 2-3: AC Electrical Characteristics (Continued) VCC = +3.3V ±5% or +2.5V ±5%; TA = -40°C to +85°C, unless otherwise shown Parameter Symbol Conditions Min Typ Max Units Notes |
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