ACE24C128B/256B/512B

Two-wire Serial EEPROM

VER 1.4

8

Current Address Read:

The internal data word address counter maintains the last address accessed during the last read or

write operation, incremented by one. This address stays valid between operations as long as the chip

power is maintained. The address "roll over" during read is from the last byte of the last memory page to

the first byte of the first page. The address "roll over" during write is from the last byte of the current page

to the first byte of the same page.

Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the

EEPROM, the current address data word is serially clocked out. The microcontroller does not respond

with an input "0" but does generate a following stop condition (see Figure 7 on page 8).

Read Operations

Random Read:

A random read requires a "dummy" byte write sequence to load in the data word address. Once the

device address word and data word address are clocked in and acknowledged by the EEPROM, the

microcontroller must generate another start condition. The microcontroller now initiates a current

address read by sending a device address with the read/write select bit high. The EEPROM

acknowledges the device address and serially clocks out the data word. The microcontroller does not

respond with a "0" but does generate a following stop condition (see Figure 8 on page 8).

Sequential Read:

Sequential reads are initiated by either a current address read or a random address read. After the

microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM

receives an acknowledge, it will continue to increment the data word address and serially clock out

sequential data words. When the memory address limit is reached, the data word address will "roll over"

and the sequential read will continue. The sequential read operation is terminated when the

microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9 on

page 8).

Figure 4: Device Address