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54F194LM Scheda tecnica(PDF) 2 Page - National Semiconductor (TI) |
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54F194LM Scheda tecnica(HTML) 2 Page - National Semiconductor (TI) |
2 / 8 page Unit LoadingFan Out Pin 54F74F Names Description UL Input IIH IIL HIGHLOW Output IOH IOL S0 S1 Mode Control Inputs 1010 20 mA b06 mA P0–P3 Parallel Data Inputs 1010 20 mA b06 mA DSR Serial Data Input (Shift Right) 1010 20 mA b06 mA DSL Serial Data Input (Shift Left) 1010 20 mA b06 mA CP Clock Pulse Input (Active Rising Edge) 1010 20 mA b06 mA MR Asynchronous Master Reset Input (Active LOW) 1010 20 mA b06 mA Q0–Q3 Parallel Outputs 50333 b 1 mA20 mA Functional Description The ’F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right shift left parallel load and hold operations Signals applied to the Select (S0 S1) inputs determine the type of operation as shown in the Mode Select Table Signals on the Select Parallel data (P0–P3) and Serial data (DSR DSL) inputs can change when the clock is in either state provid- ed only that the recommended setup and hold times with respect to the clock rising edge are observed A LOW sig- nal on Master Reset (MR) overrides all other inputs and forces the outputs LOW Mode Select Table Operating Inputs Outputs Mode MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Reset L X X X X X LLLL Hold H l l X X X q0 q1 q2 q3 Shift Left H h l X l X q1 q2 q3 L Hh l X h X q1 q2 q3 H Shift Right H l h l X X L q0 q1 q2 Hl h h X X H q0 q1 q2 Parallel Load H h h X X pn p0 p1 p2 p3 H (h) e High Voltage Level L (l) e Low Voltage Level pn (qn) e Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition X e Immaterial Logic Diagram TLF9498 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 |
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