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SN74GTL2003PWR Scheda tecnica(PDF) 8 Page - Texas Instruments |
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SN74GTL2003PWR Scheda tecnica(HTML) 8 Page - Texas Instruments |
8 / 25 page S REF D REF G REF S 1 D 1 S 2 D 2 S 3 D 3 20 2 3 4 5 19 18 17 16 SN74GTL2003 SCDS305B – FEBRUARY 2011 – REVISED JUNE 2015 www.ti.com 8 Detailed Description 8.1 Overview The SN74GTL2003 device provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage translations any voltage (0.95 V to 5 V) to any voltage (0.95 V to 5 V). When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pullup resistors. 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Provides Bidirectional Voltage Translation With No Direction Control Required Because the circuit acts essentially as a pass transistor, no direction pin is needed, as data is allowed to flow both ways. 8.3.2 Flow Through Pinout Allocated pins for input and output A on right side and input and output B on left side. Reduces the need for multi-layer board layout or long traces through system. 8 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: SN74GTL2003 |
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