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SN74AVC32T245GKER Scheda tecnica(PDF) 1 Page - Texas Instruments

Il numero della parte SN74AVC32T245GKER
Spiegazioni elettronici  32-Bit Dual-Supply Bus Transceiver
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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SN74AVC32T245GKER Scheda tecnica(HTML) 1 Page - Texas Instruments

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To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
A3
A5
H3
E5
A4
A2
H4
E2
To Seven Other Channels
3DIR
3A1
3B1
3OE
To Seven Other Channels
4DIR
4A1
4B1
4OE
J3
J5
T3
N5
J4
J2
T4
N2
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Design
SN74AVC32T245
SCES553F – MAY 2004 – REVISED JULY 2015
SN74AVC32T245 32-Bit Dual-Supply Bus Transceiver
With Configurable Voltage Translation, Level-Shifting, and Tri-State Outputs
The SN74AVC32T245 is designed for asynchronous
1 Features
communication between data buses. The device
1
Member of the Texas Instruments Widebus+™
transmits data from the A bus to the B bus or from
Family
the B bus to the A bus, depending on the logic level
Control Inputs VIH/VIL Levels Referenced to VCCA
at the direction-control (DIR) input. The output-enable
(OE) input can disable the outputs so the buses are
Voltage
effectively isolated.
VCC Isolation Feature – If Either VCC Input is at
GND, Both Ports are in the High-Impedance State
The SN74AVC32T245 is designed so that the control
pins (1DIR, 2DIR, 3DIR, 4DIR, 1OE, 2OE, 3OE, and
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-
4OE) are supplied by VCCA.
Voltage-Mode Data Communications
This device is fully specified for partial-power-down
Fully Configurable Dual-Rail Design Allows Each
applications using Ioff. The Ioff circuitry disables the
Port to Operate Over Full 1.2 V to 3.6 V Power-
outputs,
preventing
damaging
current
backflow
Supply Range
through the device when it is powered down.
Ioff Supports Partial-Power-Down Mode Operation
The VCC isolation feature ensures that if either VCC
4.6 V Tolerant I/Os
input is at GND, then both ports are in the high-
Max Data Rates
impedance state.
380 Mbps (1.8 V to 3.3 V Level-Shifting)
To ensure the high-impedance state during power up
200 Mbps (< 1.8 V to 3.3 V Level-Shifting)
or power down, OE should be tied to VCC through a
200 Mbps (Translate to 2.5 V or 1.8 V)
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
150 Mbps (Translate to 1.5 V)
driver.
100 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
Device Information(1)
JESD 78, Class II
PART NUMBER
PACKAGE
BODY SIZE (NOM)
ESD Protection Exceeds JESD 22
LFBGA (96)
13.50 mm × 5.50 mm
SN74AVC32T245
4000 V Human-Body Model (A114-A)
BGA MICROSTAR
8.50 mm × 3.50 mm
JUNIOR (96)
200 V Machine Model (A115-A)
(1) For all available packages, see the orderable addendum at
1000 V Charged-Device Model (C101)
the end of the data sheet.
2 Applications
Logic Diagram
Personal Electronics
Industrial
Enterprise
Telecom
3 Description
This 32-bit noninverting bus transceiver uses two
separate,
configurable
power-supply
rails.
The
SN74AVC32T245 device is optimized to operate with
VCCA/VCCB set from 1.4 V to 3.6 V. It is operational
with VCCA/VCCB as low as 1.2 V. The A port is
designed to track VCCA. VCCA and accepts any supply
voltage from 1.2 V to 3.6 V. The B port is designed to
track VCCB. VCCB and accepts any supply voltage from
1.2 V to 3.6 V. This allows for universal low-voltage
bidirectional translation between any of the 1.2 V,
1.5V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.


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