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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74AVC2T245

SCES692D – JUNE 2008 – REVISED FEBRUARY 2016

SN74AVC2T245 Dual-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting /

Voltage Translation and Tri-State Outputs

1

1 Features

1

•

Each Channel Has Independent Direction Control

•

•

Fully Configurable Dual-Rail Design Allows Each

Port to Operate Over the Full 1.2 V to

3.6 V Power-Supply Range

•

I/Os Are 4.6 V Tolerant

•

•

GND, Both Ports are in High-Impedance State

•

Typical Data Rates

–

500 Mbps (1.8 V to 3.3 V Level-Shifting)

–

320 Mbps (<1.8 V to 3.3 V Level-Shifting)

–

320 Mbps (Translate to 2.5 V or 1.8 V)

–

280 Mbps (Translate to 1.5 V)

–

240 Mbps (Translate to 1.2 V)

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

–

5000 V Human-Body Model (A114-A)

–

200 V Machine Model (A115-A)

–

1500 V Charged-Device Model (C101)

2 Applications

•

Personal Electronics

•

Industrial

•

Enterprise

•

Telecom

Logic Diagram (Positive Logic)

(1)

Shown for a single channel

3 Description

This dual-bit noninverting bus transceiver uses two

separate configurable power-supply rails. The A port

voltage from 1.2 V to 3.6 V. The B port is designed to

V to 3.6 V. This allows for universal low-voltage

bidirectional translation between any of the 1.2 V, 1.5

V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC2T245 is designed for asynchronous

communication between two data buses. The logic

levels of the direction-control (DIR) input and the

output-enable (OE) activate either the B-port outputs

or the A-port outputs or place both output ports into

the high-impedance mode . The device transmits data

from the A bus to the B bus when the B-port outputs

are activated and from the B bus to the A bus when

the A-port outputs are activated. The input circuitry on

both A and B ports always is active and must have a

logic HIGH or LOW level applied to prevent excess

The SN74AVC2T245 control pins (DIR1, DIR2, and

This device is fully specified for partial-power-down

outputs,

preventing

damaging

current

backflow

through the device when it is powered down.

input is at GND, both ports are in the high-impedance

state.

To ensure the high-impedance state during power up

through a pull-up resistor; the minimum value of the

resistor is determined by the current-sinking capability

of the driver.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN74AVC2T245

UQFN (10)

1.80 mm × 1.40 mm

(1) For all available packages, see the orderable addendum at

the end of the datasheet.