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SN74AUP1G57DCKT Scheda tecnica(PDF) 11 Page - Texas Instruments |
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SN74AUP1G57DCKT Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 32 page 1 2 3 6 5 4 A Y B VCC Y A B A Y B 1 2 3 6 5 4 A Y B VCC A Y B A Y B 1 2 3 6 5 4 A Y B VCC A Y B A Y B 1 2 3 6 5 4 A Y B VCC A Y B A Y B 1 2 3 6 5 4 A Y B VCC A Y B SN74AUP1G57 www.ti.com SCES503J – NOVEMBER 2003 – REVISED JUNE 2015 Table 1. Function Table (continued) INPUTS OUTPUT Y In2 In1 In0 L H H L H L L L H L H L H H L H H H H H 8.4.1 Logic Configurations Table 2 lists all the logic functions of the SN74AUP1G57. Table 2. Function Selection Table LOGIC FUNCTION FIGURE NO. 2-input AND Figure 4 2-input AND with both inputs inverted Figure 7 2-input NAND with inverted input Figure 5, Figure 6 2-input OR with inverted input Figure 5, Figure 6 2-input NOR Figure 7 2-input NOR with both inputs inverted Figure 4 2-input XNOR Figure 8 Figure 4. 2-Input AND Gate Figure 5. 2-Input NAND Gate With Inverted A Input Figure 7. 2-Input NOR Gate Figure 6. 2-Input NAND Gate With Inverted B Input Figure 8. 2-Input XNOR Gate Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SN74AUP1G57 |
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