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SN74HC165DG4 Scheda tecnica(PDF) 11 Page - Texas Instruments |
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SN74HC165DG4 Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 31 page VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOLTAGE WAVEFORMS PULSE DURATIONS th tsu 50% 50% 50% 10% 10% 90% 90% VCC VCC 0 V 0 V tr t Reference f Input Data Input 50% High-Level Pulse 50% VCC 0 V 50% 50% VCC 0 V t Low-Level w Pulse VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES 50% 50% 50% 10% 10% 90% 90% VCC VOH VOL 0 V tr t Input f In-Phase Output 50% tPLH tPHL 50% 50% 10% 10% 90% 90% VOH VOL t t r f tPHL tPLH Out-of-Phase Output NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Test Point From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT Supply Voltage (V) 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 0 10 20 30 40 50 60 70 80 D001 SN54HC165, SN74HC165 www.ti.com SCLS116H – DECEMBER 1982 – REVISED DECEMBER 2015 6.15 Typical Characteristics Figure 1. Propagation Delay vs Supply Voltage at TA = 25°C 7 Parameter Measurement Information Figure 2. Load Circuit and Voltage Waveforms Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SN54HC165 SN74HC165 |
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