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TPD3E001 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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TPD3E001 Scheda tecnica(HTML) 3 Page - Texas Instruments |
3 / 22 page IO3 VCC N.C. GND IO2 IO1 1 2 3 4 5 6 GND IO1 GND IO2 3 4 2 IO3 5 1 V CC V CC IO1 GND IO2 IO3 N.C. 3 4 2 6 5 1 TPD3E001 www.ti.com SLLS683F – JULY 2006 – REVISED OCTOBER 2015 5 Pin Configuration and Functions DRY Package DRL Package 6-Pin USON 5-Pin SOT Top View Top View DRS Package 6-Pin WSON Top View Pin Functions PIN TYPE DESCRIPTION NAME DRY NO. DRL NO. DRS NO. IOx 1, 2, 4 1, 2, 4 1, 2, 4 I/O ESD-protected channel GND 3 3 3 GND Ground Power-supply input. Bypass VCC to GND with a 0.1-μF VCC 6 5 6 Power ceramic capacitor. N.C. 5 – 5 – No connection. Not internally connected. Exposed EP – – Thermal GND Exposed thermal pad. Connect to GND or leave floating. Pad Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPD3E001 |
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