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TPD12S521DBTR Scheda tecnica(PDF) 11 Page - Texas Instruments |
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TPD12S521DBTR Scheda tecnica(HTML) 11 Page - Texas Instruments |
11 / 19 page VIA to GND Plane VIA to 5V Plane VIA to 3.3V Plane VIA to LV Plane Pin to GND Legend TPD12S521 HDMI Connector 1 11 TPD12S521 www.ti.com SLVS639F – OCTOBER 2007 – REVISED FEBRUARY 2016 Product Folder Links: TPD12S521 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated 11 Layout 11.1 Layout Guidelines • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. • Route the protected traces as straight as possible. • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 11.2 Layout Example Use external and internal ground planes and stitch them together with VIAs as close to the GND pins of TPD12S521 as possible. This allows for a low impedance path to ground so that the device can properly dissipate an ESD event. |
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