DRV

DONE

EN/

ONE_SHOT

DELAY/

M_DRV

INVALID M_DRV

TOO SHORT

VALID M_DRV

M_DRV IGNORED

DRVn HIGH

DRV

DONE

EN/

ONE_SHOT

DELAY/

M_DRV

POR

RESISTANCE

READING

MISSED

DONE

FORCED

DRVn FALLING

TPL5111

SNAS659A – JUNE 2015 – REVISED JULY 2015

www.ti.com

Device Functional Modes (continued)

7.5 Programming

7.5.1 Configuring the Time Interval with the DELAY/M_DRV Pin

The time interval between 2 adjacent DRVn pulses (rising edges, in timer mode) is selectable through an

range between 500

Ω and 170 kΩ. At least a 1% precision resistance is recommended. See Selection of the

immediately after POR.

7.5.2 Manual Power ON Applied to the DELAY/M_DRV Pin

If VDD is applied to the DELAY/M_DRV pin after startup is completed, the TPL5111 recognizes this as a manual

Power ON switch is released. A pulse on the DELAY/M_DRV pin is recognized as a valid manual Power ON only

if it lasts at least 20ms (observation time is 30ms). If DRVn is already HIGH the manual Power ON is ignored.

The manual Power ON may be implemented using a switch (momentary mechanical action).

Figure 11. Manual Power ON in Timer Mode

10

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