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Motore di ricerca datesheet componenti elettronici |
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DAC5681ZIRGCT Scheda tecnica(PDF) 9 Page - Texas Instruments |
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DAC5681ZIRGCT Scheda tecnica(HTML) 9 Page - Texas Instruments |
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9 / 61 page  DAC5681Z www.ti.com SLLS865G – AUGUST 2007 – REVISED NOVEMBER 2015 Electrical Characteristics — AC Specification (1) (continued) Over recommended operating free-air temperature range, AVDD, IOVDD = 3.3 V, CLKVDD, DVDD = 1.8 V, IOUTFS = 20 mA, 4:1 transformer output termination, 50- Ω doubly terminated load (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE (continued) 1X2, PLL off, CLKIN = 500 MHZ, 75 Single tone, 0 dBFS, IF = 20.1 MHz 1X2, PLL off, CLKIN = 1000 MHZ, 70 Single tone, 0 dBFS, IF = 20.1 MHz 1X2, PLL off, CLKIN = 1000 MHZ, 66 Single tone, 0 dBFS, IF = 70.1 MHz SNR Signal-to-noise ratio dBc 1X4, PLL off, CLKIN = 1000 MHZ, 60 Single tone, 0 dBFS, IF = 180 MHz 1X2 , PLL off, CLKIN = 1000 MHZ, 60 Single tone, 0 dBFS, IF = 300.2 MHz 1X2, PLL off, CLKIN = 1000 MHZ, Four tone, each – 12 dBFS, 73 IF = 24.7, 24.9, 25.1 and 25.3 MHz 1X2, PLL off, CLKIN = 1000 MHZ, 88 IF = 20.1 and 21.1 MHz Third-order two-tone 1X2, PLL off, CLKIN = 1000 MHZ, intermodulation IMD3 75 dBc IF = 70.1 and 71.1 MHz (each tone at –6 dBFS) 1X2, PLL off, CLKIN = 1000 MHZ, 67 IF = 150.1 and 151.1 MHz Four-tone intermodulation 1X2, PLL off, CLKIN = 1000 MHz, IMD 64 dBc (each tone at –12 dBFS) IF = 298.4, 299.2, 300.8 and 301.6 MHz Single carrier, baseband, 1X2, PLL off, 80 83 CLKIN = 983.04 MHz Single carrier, IF = 180 MHz, 1X2, PLL off, 73 CLKIN = 983.04 MHz ACLR(2) Adjacent channel leakage ratio dBc Four carrier, IF = 180 MHz, 1X2, PLL off, 68 CLKIN = 983.04 MHz Four carrier, IF = 275 MHz, 1X2, PLL off, 66 CLKIN = 983.04 MHz 50-MHz offset, 1-MHz BW, Single Carrier, baseband, 93 1X2, PLL off, CLKIN = 983.04 Noise floor(3) dBc 50-MHz offset, 1-MHz BW, Four Carrier, baseband, 85 1X2, PLL off, CLKIN = 983.04 ANALOG OUTPUT fCLK Maximum output update rate 1000 MSPS ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10.4 ns DAC output is updated on falling edge of DAC clock. tpd Output propagation delay 2.5 ns Does not include Digital Latency tr(IOUT) Output rise time 10% to 90% 220 ps tf(IOUT) Output fall time 90% to 10% 220 ps No interpolation, PLL Off 76 DAC Digital Latency x2 interpolation, PLL Off 158 clock cycles x4 interpolation, PLL Off 289 IOUT current settling to 1% of IOUTFS. Measured from DAC Wake-up Time 80 μs SDENB; Register 0x06, toggle Bit 4 from 1 to 0. Power-up Time IOUT current settling to less than 1% of IOUTFS. Measured DAC Sleep Time 80 μs from SDENB; Register 0x06, toggle Bit 4 from 0 to 1. (2) W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF. TESTMODEL 1, 10 ms (3) Carrier power measured in 3.84-MHz BW. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DAC5681Z |
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