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TS12011 Scheda tecnica(PDF) 10 Page - Silicon Laboratories |
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TS12011 Scheda tecnica(HTML) 10 Page - Silicon Laboratories |
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10 / 18 page  TS12011/TS12012 Page 10 TS12011/12 Rev. 1.0 change, the comparator stays active and waits for the crossing, at which point it will latch in its final state. An internal POR circuit ensures that the latch powers up in the “comparator active” state if LHDET is low when VDD is first applied. Latch Truth Table – TS12011 LHDET CMPOUT initial state CMPIN+ to CMPIN- difference voltage CMPOUT HIGH X N/A Normal operation LOW HIGH X HIGH (latched) LOW LOW negative LOW (comparator active) LOW LOW positive HIGH (latched) X = Don’t Care Latch Truth Table – TS12012 LHDET CMPOUT initial state CMPIN+ to CMPIN- difference voltage CMPOUT HIGH X N/A Normal operation LOW LOW X LOW (latched) LOW HIGH positive HIGH (comparator active) LOW HIGH negative LOW (latched) X = Don’t Care Reference The TS12011 and TS12012 on-board 0.58V ±4.5% reference voltage can source and sink 0.1µA and 0.1µA of current and can drive a capacitive load less than 50pF and greater than 50nF with a maximum capacitive load of 250nF. The higher the capacitive load, the lower the noise on the reference voltage and the longer the time needed for the reference voltage to respond and become available on the REFOUT pin. With a 250nF capacitive load, the reference voltage will settle to within specifications in approximately 20ms. Op Amp The TS12011 and TS12012 have a unity-gain stable op-amp with a GBWP of 15kHz, a slew rate of 6V/ms, and can drive a capacitive load up to 50pF. The common mode input voltage range extends from VSS to VDD and the input bias current and offset current are less than 20nA and 2nA, respectively. Op-Amp Stability The TS12011 and TS12012 op-amp is able to drive up to 50pF of capacitive load and still maintain stability in a unity-gain configuration with a 15kHz GBWP and a phase margin of 70 degrees with a 100k Ω//20pF output load. Though the TS12011 and TS12012 address low frequency applications, it is essential to perform good layout techniques in order to minimize board leakage and stray capacitance, which is of a concern in low power, high impedance circuits. For instance, a 10M Ω resistor coupled with a 1pF stray capacitance can lead to a pole at approximately 15kHz, which is the GBWP of the device. If stray capacitance is unavoidable, a feedback capacitor can be placed in parallel with the feedback resistor. APPLICATIONS INFORMATION Comparator Hysteresis As a result of circuit noise or unintended parasitic feedback, many analog comparators often break into oscillation within their linear region of operation especially when the applied differential input voltage approaches 0V (zero volt). Externally-introduced hysteresis is a well-established technique for stabilizing analog comparator behavior and requires external components. As shown in Figure 1, adding comparator hysteresis creates two trip points: VTHR (for the rising input voltage) and VTHF (for the falling input voltage). The hysteresis band (VHB) is defined as the voltage difference between the two trip points. When a comparator’s input voltages are equal, hysteresis effectively forces one comparator input to move quickly past the other input, moving the input out of the region where oscillation occurs. Figure 1 illustrates the case in which an IN- input is a fixed voltage and an IN+ is varied. If the input signals were reversed, the figure would be the same with an inverted output. To save cost and external pcb area, an internal ±7.5mV hysteresis circuit was added to the TS12011 and TS12012. |
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