AN349

4

Rev. 0.1

2. Hardware Description

2.1. Power, Initialization Sequence, and Busmode Selection

Figure 1. Initialization Sequence

2.1.1. Hardware Initialization

The FM tuner device is capable of communicating using either a 3-wire or 2-wire interface. The selection of this

interface is made during the reset sequence.

Figure 1 demonstrates the sequencing of hardware events relative to reset. Figure 2 combines this information

with the setting of the ENABLE and DISABLE bits to better describe the possible combinations. The following steps

should be used to initialize the device properly.

1. Supply VA and VD.

2. Supply VIO while keeping the RST pin low. Note that power supplies may be sequenced in any order (steps 1

and 2 may be reversed).

3. Configure the SENB pin for bus mode selection. See Figure 3, “Powerup, Powerdown, and Reset Flowchart,”

on page 6.

4. Set the RST pin high. The device registers may now be read and written.

5. Provide RCLK. A delay may be necessary for some external oscillator circuits to ensure that the

oscillator has stabilized. Please determine the necessary stabilization time for the clock source in the

system.

Note: The Si4708/09 does not offer an internal oscillator option.

6. Set the ENABLE bit high and the DISABLE bit low to power up the device.

2.1.2. Hardware Powerdown

A powerdown mode is available to reduce power consumption when the part is idle. Setting both the ENABLE bit

high and the DISABLE bit high starts the powerdown sequence. This disables analog and digital circuitry while

maintaining register configuration and keeping the bus active. Note that the device automatically sets the ENABLE

bit low after the internal powerdown sequence completes. Setting the ENABLE bit low directly will cause the device

to partially powerdown and should be avoided. See Figure 2. Setting the ENABLE bit high and the DISABLE bit low

will bring the device out of powerdown mode and resume normal operation. Refer to Figure 1 for more information.

To power down the device:

1. Set Register 4 [5:4], [3:2], and [1:0] to 0b10. This step is required for the Si4708/09 to ensure VIO

powerdown mode current meets data sheet specifications.

2. Set the ENABLE bit high and the DISABLE bit high to place the device in powerdown mode. Note that all

register states are maintained so long as VIO is supplied and the RST pin is high.

VA,VD Supply

RCLK Pin

ENABLE Bit

12

34

5

RST Pin

VIO Supply