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CDCE913PWRG4 Scheda tecnica(PDF) 10 Page - Texas Instruments

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Il numero della parte CDCE913PWRG4
Spiegazioni elettronici  Programmable 1-PLL VCXO Clock Synthesizer
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Produttore elettronici  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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EEPROM
Xin/CLK
Xout
VDD
GND
InputClock
Vctr
S0
Programming
and
SDA/SCL
Register
Y2
Y1
Y3
LV
CMOS
Pdiv1
10-Bit
LV
CMOS
Pdiv3
7-Bit
Pdiv2
7-Bit
PLL Bypass
LV
CMOS
PLL 1
withSSC
S1/SDA
S2/SCL
VCXO
XO
LVCMOS
VDDOUT
CDCE913, CDCEL913
SCAS849F – JUNE 2007 – REVISED APRIL 2015
www.ti.com
8 Detailed Description
8.1 Overview
The CDCE913 and CDCEL913 devices are modular PLL-based, low-cost, high-performance, programmable
clock synthesizers, multipliers, and dividers. They generate up to three output clocks from a single input
frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using the
integrated configurable PLL.
The CDCx913 has separate output supply pins, VDDOUT, which is 1.8 V for CDCEL913 and 2.5 V to 3.3 V for
CDCE913.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load
capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF.
Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control
signal, that is, the PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, Bluetooth,
Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input
frequency.
The PLL supports spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking, which
is a common technique to reduce electromagnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically
adjusted to achieve high stability and optimized jitter transfer characteristics.
The device supports nonvolatile EEPROM programming for easy customization of the device to the application. It
is preset to a factory default configuration (see Default Device Configuration). It can be reprogrammed to a
different application configuration before PCB assembly, or reprogrammed by in-system programming. All device
settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC
setting for lowering EMI, or control other features like outputs disable to low, outputs 3-state, power down, PLL
bypass, and so forth).
The CDCx913 operates in a 1.8-V environment. It operates in a temperature range of –40° C to 85° C.
8.2 Functional Block Diagram
10
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Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: CDCE913 CDCEL913


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