Si53322

Rev. 1.0

5

Figure 1. Differential Measurement Method Using a Balun

Table 6. Additive Jitter, Differential Clock Input

Input1,2

Output

Additive Jitter

(fs rms, 12 kHz to

20 MHz)3

Freq

(MHz)

Clock Format

Amplitude

(Single-Ended,

Peak-to-Peak)

Differential

20%-80% Slew

Rate (V/ns)

Clock Format

Typ

Max

3.3

725

Differential

0.15

0.637

LVPECL

55

95

3.3

156.25

Differential

0.5

0.458

LVPECL

160

185

2.5

725

Differential

0.15

0.637

LVPECL

55

95

2.5

156.25

Differential

0.5

0.458

LVPECL

145

185

Notes:

1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock

Buffer’s Additive Jitter Performance” for more information.

2. AC-coupled differential inputs.

3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.

Table 7. Additive Jitter, Single-Ended Clock Input

Input1,2

Output

Additive Jitter

(fs rms, 12 kHz to

20 MHz)3

Freq

(MHz)

Clock Format

Amplitude

(single-ended,

peak to peak)

SE 20%-80%

Slew Rate

(V/ns)

Clock Format

Typ

Max

3.3

156.25

Single-ended

2.18

1

LVPECL

160

185

2.5

156.25

Single-ended

2.18

1

LVPECL

145

185

Notes:

1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock

Buffer’s Additive Jitter Performance” for more information.

2. DC-coupled single-ended inputs.

3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.

PSPL 5310A

CLKx

/CLKx

50

50

Balun

50ohm

AG E5052 Phase Noise

Analyzer

Si533xx

DUT

PSPL 5310A

CLK SYNTH

SMA103A

Balun