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SI53159 Scheda tecnica(PDF) 6 Page - Silicon Laboratories |
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SI53159 Scheda tecnica(HTML) 6 Page - Silicon Laboratories |
6 / 23 page Si53159 6 Rev. 1.1 Enable/Disable and Setup Clock Stabilization from Power-Up TSTABLE —— 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Table 3. Absolute Maximum Conditions Parameter Symbol Condition Min Typ Max Unit Main Supply Voltage VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Extended Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 22 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 30 °C/W ESD Protection (Human Body Model) ESDHBM JEDEC (JESD 22 - A114) 2000 — — V Flammability Rating UL-94 UL (Class) V–0 Moisture Sensitivity Level MSL JEDEC (J-STD-020) 2 Note: Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. Table 2. AC Electrical Specifications (Continued) Parameter Symbol Condition Min Typ Max Unit Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. |
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