SI5347 datasheet(11/59 Pages) SILABS

Il numero della parte	SI5347

Spiegazioni elettronici	DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS

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Produttore elettronici	SILABS [Silicon Laboratories]

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Si5347/46

Rev. 1.1

11

Table 6. LVCMOS Clock Output Specifications

(VDD = 1.8 V ±5%, VDDA =3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Frequency

fOUT

0.0001

—

250

MHz

Duty Cycle

DC

fOUT <100 MHz

47

—

53

%

100 MHz < fOUT < 250 MHz

44

—

55

Output-to-Output Skew

TSK

LVCMOS outputs

—

100

ps

Output Voltage High1, 2, 3

VOH

VDDO = 3.3 V

OUTx_CMOS_DRV=1

IOH = –10 mA

VDDO x

0.75

——

V

OUTx_CMOS_DRV=2

IOH = –12 mA

—

OUTx_CMOS_DRV=3

IOH = –17 mA

—

VDDO = 2.5 V

OUTx_CMOS_DRV=1

IOH = –6 mA

VDDO x

0.75

——

V

OUTx_CMOS_DRV=2

IOH = –8 mA

—

OUTx_CMOS_DRV=3

IOH = –11 mA

—

VDDO = 1.8 V

OUTx_CMOS_DRV=2

IOH = –4 mA

VDDO x

0.75

——

V

OUTx_CMOS_DRV=3

IOH = –5 mA

—

Notes:

1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer

to the Si5347/46 Family Reference Manual for more details on register settings.

2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.

3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3.

DC Test Configuration

Zs

IOL/IOH

VOL/VOH

50

OUT

IDDO

Trace length 5

inches

50

4.7 pF

499



56



4.7 pF

499



56



50

 Scope Input

50

 Scope Input

0.1 µF

LVCMOS Output Test Configuration

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