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SI5335 Scheda tecnica(PDF) 10 Page - Silicon Laboratories |
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SI5335 Scheda tecnica(HTML) 10 Page - Silicon Laboratories |
10 / 47 page Si5335 10 Rev. 1.4 Table 8. Jitter Specifications, Clock Generator Mode (Loop Bandwidth = 1.6 MHz)1,2,3 (VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit GbE Random Jitter (12kHz–20MHz)4 JGbE CLKIN = 25 MHz All CLKn at 125 MHz5 — 0.7 1 ps RMS GbE Random Jitter (1.875–20 MHz) RJGbE CLKIN = 25 MHz All CLKn at 125 MHz5 — 0.38 0.79 ps RMS OC-12 Random Jitter (12 kHz–5 MHz) JOC12 CLKIN = 19.44 MHz All CLKn at 155.52 MHz5 — 0.7 1 ps RMS PCI Express 1.1 Common Clocked (with spread spectrum) Total Jitter6 — 20.1 33.6 ps pk-pk PCI Express 2.1 Common Clocked (no spread spec- trum) RMS Jitter6, 10 kHz to 1.5 MHz — 0.15 1.47 ps RMS RMS Jitter6, 1.5 MHz to 50 MHz — 0.58 0.75 ps RMS PCI Express 3.0 Common Clocked (no spread spectrum) RMS Jitter6 — 0.15 0.45 ps RMS PCIe Gen 3 Separate Reference No Spread, SRNS PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz — 0.11 0.32 ps RMS PCIe Gen 4, Common Clock PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz — 0.15 0.45 ps RMS Period Jitter JPER N = 10,000 cycles7 — 10 30 ps pk-pk Notes: 1. All jitter measurements apply for LVDS/HCSL/LVPECL/CML output format with a low noise differential input clock and are made with an Agilent 90804 oscilloscope. All RJ measurements use RJ/DJ separation. 2. All jitter data in this table is based upon all output formats being differential. When single-ended outputs are used, there is the potential that the output jitter may increase due to the nature of single-ended outputs. If your configuration implements any single-ended output and any output is required to have jitter less than 2 ps rms, contact Silicon Labs for support to validate your configuration and ensure the best jitter performance. In many configurations, CMOS outputs have little to no effect upon jitter. 3. For best jitter performance, keep the single-ended clock input slew rates at pins 1 and 2 greater that 1.0 V/ns and the differential clock input slew rates greater than 0.3 V/ns. 4. DJ for PCI and GbE is < 5 ps pp 5. Output MultiSynth in Integer mode. 6. All output clocks 100 MHz HCSL format. Jitter is from the PCIE jitter filter combination that produces the highest jitter. See AN562 for details. Jitter is mesured with the Intel Clock Jitter Tool, Ver.1.6.4. 7. For any output frequency > 10 MHz. 8. Measured in accordance with JEDEC standard 65. 9. Rj is multiplied by 14; estimate the pp jitter from Rj over 212 rising edges. 10. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 11. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. |
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