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EZR32LG230F128R55G Scheda tecnica(PDF) 10 Page - Silicon Laboratories |
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EZR32LG230F128R55G Scheda tecnica(HTML) 10 Page - Silicon Laboratories |
10 / 87 page 3.2 Configuration Summary The features of the EZR32LG230 are a subset of the feature set described in the EZR32LGReference Manual. The table below de- scribes device specific implementation of the features. Table 3.2. Configuration Summary Module Configuration Pin Connections Cortex-M3 Full configuration NA DBG Full configuration DBG_SWCLK, DBG_SWDIO, DBG_SWO MSC Full configuration NA DMA Full configuration NA RMU Full configuration NA EMU Full configuration NA CMU Full configuration CMU_OUT0, CMU_OUT1 WDOG Full configuration NA PRS Full configuration NA I2C0 Full configuration I2C0_SDA, I2C0_SCL I2C1 Full configuration I2C1_SDA, I2C1_SCL USARTRF0 Full configuration with IrDA US0_TX, US0_RX, US0_CLK, US0_CS USART1 Full configuration with I2S US1_TX, US1_RX, US1_CLK, US1_CS USART2 Full configuration with I2S US2_TX, US2_RX, US2_CLK, US2_CS UART0 Full configuration U0_TX, U0_RX UART1 Full configuration U1_TX, U1_RX LEUART0 Full configuration LEU0_TX, LEU0_RX LEUART1 Full configuration LEU1_TX, LEU1_RX TIMER0 Full configuration with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 Full configuration TIM1_CC[2:0] TIMER2 Full configuration TIM2_CC[2:0] TIMER3 Full configuration TIM3_CC[2:0] RTC Full configuration NA BURTC Full configuration NA LETIMER0 Full configuration LET0_O[1:0] PCNT0 Full configuration, 16-bit count register PCNT0_S[1:0] PCNT1 Full configuration, 8-bit count register PCNT1_S[1:0] PCNT2 Full configuration, 8-bit count register PCNT2_S[1:0] ACMP0 Full configuration ACMP0_CH[7:0], ACMP0_O ACMP1 Full configuration ACMP1_CH[7:0], ACMP1_O VCMP Full configuration NA ADC0 Full configuration ADC0_CH[7:0] DAC0 Full configuration DAC0_OUT[1:0] EZR32LG230 Data Sheet System Overview silabs.com | Smart. Connected. Energy-friendly. Rev. 1.1 | 9 |
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