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FAN54300 Scheda tecnica(PDF) 8 Page - Fairchild Semiconductor

Il numero della parte FAN54300
Spiegazioni elettronici  USB-Compliant, Dual-Power Input, Single-Cell, Li-Ion Switching Charger with USB-OTG Boost Regulator
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN54300 Scheda tecnica(HTML) 8 Page - Fairchild Semiconductor

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© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN54300
• Rev. 1.0.4
8
Electrical Specifications
Unless otherwise specified: circuit of Figure 1, recommended operating temperature range for TJ and TA, VBUS or VIN = 5.0 V,
HZ1, HZ2, OPA_MODE = 0, (Charger Mode). SCL, SDA, OTG = 0 or 1.8 V. Typical values are for TJ = 25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Power Supplies
IVBUS
VBUS Current
PWM Switching, Open Battery, TE=0
33
mA
PWM Not Switching (VBAT > VOREG)
3.6
mA
0°C < TJ < 85°C, HZ1 = 1, VBAT > VLOWV
350
500
µA
0°C < TJ < 85°C, HZ1 = 1, VBAT <
VLOWV, 32S Mode
350
500
µA
IVIN
VIN Current
PWM Switching, Open Battery, TE=0
33
mA
PWM Not Switching (VBAT>VOREG)
2.6
mA
0°C < TJ < 85°C, HZ2 = 1, VIN > VLOWV
350
500
µA
0°C < TJ < 85°C, HZ2 = 1, VIN < VLOWV,
32S Mode
350
500
µA
IBAT
Battery Discharge Current in
High-Z Mode
0°C < TJ < 85°C, HZ1=HZ2 = 1 or
DIS=1, VBAT = 4.2 V
20
µA
0°C < TJ < 85°C, VBAT = 4.2 V, VIN =
VBUS = Open or GND, HZ1=HZ2=1,
SDA = SCL = 1.8 V, No I
2C Traffic
30
µA
Charger Voltage Regulation
VOREG
Charge Voltage Range
3.5
4.4
V
Charge Voltage Accuracy
TA = 25°C
–0.5
+0.5
%
TJ = 0 to 125°C
–1
+1
%
Charging Current Regulation
IOCHRG
Output Charge Current Range
VLOWV < VBAT < VOREG,
VBUS > VSLP, RSENSE = 68 m
550
1500
mA
Charge Current Accuracy
Across RSENSE
20 mV < VIREG < 40 mV
92
97
102
% of
Setting
VIREG > 40 mV
94
97
100
Weak-Battery Detection
VLOWV
Weak-Battery Threshold
Accuracy
3.4 < VLOWV < 3.7
-5
+5
%
Weak Battery Deglitch Time
Rising Voltage, 2 mV Overdrive
30
ms
Logic Levels: DIS, SDA, SCL, OTG
VIH
HIGH-Level Input Voltage
1.05
V
VIL
LOW-Level Input Voltage
0.4
V
IIN
Input Bias Current
Input Tied to GND or VBAT
0.01
1.00
µA
Charge Termination Detection
I(TERM)
Termination Current Range
VBAT > VOREG – VRCH, VBUS > VSLP,
RSENSE = 68 m
50
400
mA
Termination Current Accuracy
[VCSIN – VBAT ] from 3 mV to 20 mV
–25%
+25%
[VCSIN – VBAT ] from 20 mV to 40 mV
–5%
+5%
Termination Current Deglitch
Time
2 mV Overdrive
30
ms
Continued on the following page…


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