© 2013 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN6757

• Rev. 1.0.1

3

Z - Plant Code

X - 1-Digit Year Code

Y - 1-Digit Week Code

TT - 2-Digit Die Run Code

T - Package Type (M=SOP)

M - Manufacture Flow Code

Marking Information

Figure 3. Top Mark

Pin Configuration

SOP-8

GND

SENSE

VDD

RT

GATE

HV

NC

FB

1

8

7

6

5

4

2

3

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Description

1

GND

Ground. This pin is used for the ground potential of all the pins. A 0.1 µF decoupling capacitor

placed between VDD and GND is recommended.

2

FB

Feedback. The output voltage feedback information from the external compensation circuit is fed

into this pin. The PWM duty cycle is determined from this pin and the current-sense signal from

Pin 6. The FAN6757 performs open-loop protection: if the FB voltage is higher than a threshold

voltage (around 4.6 V) for more than 57.5 ms, the controller latches off the PWM.

3

NC

No connection

4

HV

High-Voltage Startup. This pin is connected to the line input or bulk capacitor, via 200 k

Ω

resistors, to achieve brownout and high/low line compensation. If the voltage of the HV pin is

lower than the brownout voltage (AC line peak voltage less than 100 V) and lasts for 65 ms,

PWM output turns off. High/low line compensation dominates the OCP level and cycle-by-cycle

current limit, to solve the unequal OCP level and power-limit problems under universal input.

5

RT

Over-Temperature Protection. An external NTC thermistor is connected from this pin to the

GND pin. The impedance of the NTC thermistor decreases at high temperatures. Once the

voltage of the RT pin drops below the threshold voltage, the controller latches off the PWM. If the

RT pin is not connected to an NTC resistor for over-temperature protection, it is recommended to

place one 100

kΩ resistor to ground to prevent from noise interference. This pin is limited by an

internal clamping circuit.

6

SENSE

Current Sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle

current limiting.

7

VDD

OVP trigger point.

8

GATE

Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped

below 14.5 V.

ZXYTT

6757

TM