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KAT1108E Scheda tecnica(PDF) 4 Page - Integrated Device Technology |
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KAT1108E Scheda tecnica(HTML) 4 Page - Integrated Device Technology |
4 / 17 page 6-bit Digital Step Attenuator 400 to 4000 MHz IDTF1953 Glitch-Free TM Digital Step Attenuator 4 Rev2 April2014 F1953 DATASHEET SERIAL CONTROL Serial mode is selected when VMODE is pulled high (> VIH), In serial mode the F1953 attenuation setting is programmed via the 3 wire bus (LE, CLK, DATA). In serial mode data is clocked in MSB first. Note the timing diagram below. Note – The IDTF1953 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being programmed. When Latch enable is high (> VIH), the CLK input is disabled and DATA will not be clocked into the shift register. It is recommended that LE be pulled high (> VIH) when the device is not being programmed. SERIAL REGISTER DEFAULT CONDITION If the device is powered up in Serial Mode, the device will default to whatever attenuation state is defined by the six parallel data input pins D5,D4,D3,D2,D1,D0 thus allowing any attenuation setting to be specified as the power up state. SERIAL REGISTER TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue) SERIAL REGISTER TIMING TABLE Interval Symbol Description Min Spec Max Spec Units A From rising edge of Vmode to rising edge of CLK for D5 20 nsec B Clock high pulse width 10 nsec C From rising edge of CLK pulse for D0 to LE rising edge 10 nsec D LE minimum pulse width 30 nsec Data Word 6 bits D5 D4 D0 D3 D1 D2 8 dB CLK DATA Data Word Latched into Active Register LSB 16 dB 1 2 3 4 5 6 7 8 9 4 dB 2 dB 1 dB 0.5 dB MSB LE VMODE Spec Interval A B C D Polarity: 1 = Attenuation switched IN 0 = Attenuation switched OU T Time |
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