KAT1108E datasheet(4/17 Pages) IDT

Il numero della parte	KAT1108E

Spiegazioni elettronici	7-bit 0.25 dB Digital Step Attenuator

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Produttore elettronici	IDT [Integrated Device Technology]

Homepage	http://www.idt.com

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7-bit 0.25 dB Digital Step Attenuator

150 MHz to 4000 MHz

Glitch-Free

TM Digital Step Attenuator

4

Rev1 March 2012

IDTF1950

DATASHEET

SERIAL CONTROL MODE

Serial mode is selected by floating VMODE (pin3) or pulling it to a voltage > VIH. In serial mode data is clocked in LSB

first. Note the timing diagram below.

Note – The IDTF1950 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device

is not being programmed. When Latch enable is high (> VIH), the CLK input is disabled and DATA will not be clocked

into the shift register. It is recommended that LE be pulled high (> VIH) when the device is not being programmed.

SERIAL REGISTER TIMING DIAGRAM: (Note the Timing Spec Intervals in Blue)

SERIAL MODE DEFAULT CONDITION:

When the device is powered up it will default to the Maximum Attenuation setting as described below:

Note that for the F1950 in all cases (High or 1) = Attenuation Stepped IN. (0 or Low) = Attenuation Stepped OUT.

SERIAL MODE TIMING TABLE:

Interval

Symbol

Description

Min

Spec

Max

Spec

Units

A

Parallel to Serial Setup Time

100

nsec

B

Serial Data Hold Time

10

nsec

C

LE delay from final serial clock rising edge

10

nsec

Data Word 8 bits

D0

D1

D5

D2

D4

D3

0.5 dB

CLK

DATA

Data Word

Latched into

Active Register

LSB

D7

0.25 dB

1

2

3

4

5

6

7

8

9

1 dB

2 dB

4 dB

8 dB

16 dB

MSB

X

D6

RSV

LE

VMODE

Spec

Interval

A

B

C

Time

Default Register Settings

1

0

1

D7

D6

D2

D5

D3

D4

RSV

D0

MSB

D1

LSB

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