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STK672-632AN-E Scheda tecnica(PDF) 6 Page - ON Semiconductor

Il numero della parte STK672-632AN-E
Spiegazioni elettronici  2-phase Stepper Motor Driver
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Produttore elettronici  ONSEMI [ON Semiconductor]
Homepage  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

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STK672-632AN-E
No.A2297-6/28
Sample Application Circuit
Precautions
[GND wiring]
To reduce noise on the 5V/24V system, be sure to place the GND of C01 in the circuit given above as close as possible
to Pin 2 and Pin 6 of the hybrid IC.
In addition, in order to set the current accurately, the GND side of RO2 of Vref must be connected to the shared ground
terminal used by the Pin 18 (S.G) GND, P.G1 and P.G2.
[Input pins]
If VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to S. GND,
Pin 18. Measures must also be taken so that a voltage equal to or greater than VDD is not input.
Do not wire by connecting the circuit pattern on the P.C.B side to Pins 7, 8, or 11 on the N.C. shown in the internal
block diagram.
 Apply 2.5V high level input to pins 10, 12, 13, 14, 15, and 17.
 Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 14, 15, and 17
are used as inputs, a 1 to 20k
 pull-up resistor (to VDD) must be used.
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down to
less than 0.8V at Low level (less than 0.8V at Low level when IOL=5mA).
[Current setting Vref]
Considering the specifications for the Vref input bias current IIB, we recommend a value 1k
 or less for R02.
If the motor current is temporarily reduced, the circuit given below(STK672-630AN/-632AN-E: IOH>0.2A)
is recommended.
5V
R01
R02
R3
5V
R02
R3
Vref
Vref
R01
STK672
-63xAN-E
+
9
12
10
17
13
15
14
16
19
18
6
2
5
4
1
3
VDD(5V)
CLOCK
MODE1
MODE2
CWB
ENABLE
RESETB
FAULT
A
AB
B
BB
Vref
R01
R03
R02
S.G
P.G1
P.G2
P.GND
VCC
24V
C01
at least 100
F
2 phase stepper motor driver
+
C02
10
F


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