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DM54175J Scheda tecnica(PDF) 1 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Il numero della parte DM54175J
Spiegazioni elettronici  Hex/Quad D Flip-Flops with Clear
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Produttore elettronici  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
Logo NSC - National Semiconductor (TI)

DM54175J Scheda tecnica(HTML) 1 Page - National Semiconductor (TI)

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TLF6557
June 1989
54174DM54174DM74174 54175DM54175DM74175
HexQuad D Flip-Flops with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic All have a direct clear
input and the quad (175) version features complementary
outputs from each flip-flop
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the positive-
going edge of the clock pulse Clock triggering occurs at a
particular voltage level and is not directly related to the tran-
sition time of the positive-going pulse When the clock input
is at either the high or low level the D input signal has no
effect at the output
Features
Y
174 contains six flip-flops with single-rail outputs
Y
175 contains four flip-flops with double-rail outputs
Y
Buffered clock and direct clear inputs
Y
Individual data input to each flip-flop
Y
Applications include
Bufferstorage registers
Shift registers
Pattern generators
Y
Typical clock frequency 40 MHz
Y
Typical power dissipation per flip-flop 38 mW
Y
Alternate MilitaryAerospace device (54174 54175) is
available Contact a National Semiconductor Sales Of-
ficeDistributor for specifications
Connection Diagrams
Dual-In-Line Package
TLF6557 – 1
Order Number 54174DMQB 54174FMQB DM54174J
DM54174W or DM74174N
See NS Package Number J16A N16E or W16A
Dual-In-Line Package
TLF6557 – 2
Order Number 54175DMQB 54175FMQB DM54175J
DM54175W or DM74175N
See NS Package Number J16A N16E or W16A
Function Table (Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
Q
Q
LX
X
L
H
H
u
HH
L
H
u
LL
H
HL
X
Q0
Q0
H e High Level (steady state)
L e Low Level (steady state)
X e Don’t Care
u e Transition from low to high level
Q0 e The level of Q before the indicated steady-state input conditions were established
e
175 only
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A


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