LA4815VH

No.A1374-6/15

Notes on Using the IC

1. Voltage gain settings (Pins 4 and 11)

The voltage gain of the power amplifier is fixed by the internal resistors.

• Pins 4 and 11 be left open : Approximately 26dB

• Pins 4 and 11 connected to GND : Approximately 39.5dB

Note that the voltage gain can be changed using two resistors. (See Fig. 1)

• Voltage gain setting : According to the resistor connected between Pin 4 and Pin 12 (GND1)

* Voltage gain = 20log (20

× (625 + Rvg1)/(125 + Rvg1))

• Output DC voltage setting : According to the resistor connected between Pin 11 and Pin 12 (GND1)

* Rvg1 = Rvg2 must be satisfied.

In addition, the voltage gain can also be lowered to approximately 20dB (when using 5V or 6V power supply) by an

application such as shown in Fig. 2 below.

• Voltage gain setting : According to the resistor connected between Pin 4 and Pin 1 (OUT)

* Voltage gain = 20log (20

× (125 + Rvg3)/(10,125 + Rvg3))

• Output DC voltage setting : According to the resistor connected between Pin 11 and Pin 2 (VCC)

* Set the resistor values so that the Pin 5 (OUT) DC voltage is approximately half the supply voltage.

Example : When Rvg3 = 10kΩ, Rvg4 = 22kΩ(when VCC = 6V)

However, note that using this method to greatly lower the voltage gain deteriorates the characteristics, so the voltage

gain should be lowered only to approximately 20dB. In addition, when using a high supply voltage (7V or more), the

clipped waveform may invert, so this voltage gain reduction method must not be used in these cases.

Figure 1

Figure 2

2. Signal source impedance : rg

As mentioned above, since the input coupling capacitor Cin affects the ripple rejection ratio, the signal source

impedance value rg, which is associated with this capacitor, also affects the ripple rejection ratio, so rg should be as

small as possible. Therefore, when attenuating the signal at the Cin front end as shown in Fig. 4, the constants should be

set in consideration of these characteristics. Using the smallest resistor Rg1 value possible is recommended.

In addition, when setting the signal level, the voltage gain should be set on the LA4815VH side and the input front-end

should be configured using only the input coupling capacitor, Cin, as shown in Fig. 5 in order to maximize the ripple

rejection ratio.

Figure 4

Figure 3

Figure 5

LA4815VH

Rvg2

Rvg1

GAIN2

OUT

VCC

GND1

GAIN1

LA4815VH

Rvg4

Rvg3

GAIN2

OUT

VCC

GND1

GAIN1

1

2

4

12

11

1

2

4

12

11

Vbias

100k

Ω

+

-

Pre-Amp

Rg2

Cin

Rg1

rg

other IC

ro

LA4815VH

Cin

other IC

ro

LA4815VH

Cin

IN

OUT

IN

13

13

OUT

IN

13