1

2

3

4

5

8

7

6

FB

PGATE

ISEN

GND

VCC

ADJ

RT

VIN

8

7

6

5

4

3

2

1

Exposed Pad on Bottom

Connect to Ground

FB

GND

ADJ

PGATE

ISEN

VCC

RT

VIN

1

2

3

4

5

8

7

6

Exposed Pad on Bottom

Connect to Ground

FB

PGATE

ISEN

GND

VCC

ADJ

RT

VIN

LM25085, LM25085-Q1

www.ti.com

SNVS593J – OCTOBER 2008 – REVISED NOVEMBER 2014

5 Pin Configuration and Functions

HVSSOP-PowerPad™

WSON

8-Lead DGN0008A

8-Lead NGQ0008A

Top View

Top View

VSSOP

8-Lead DGK0008A

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

Current Limit Adjust - The current limit threshold is set by an external resistor from VIN to ADJ in

ADJ

1

I

On-time control and shutdown - An external resistor from VIN to RT sets the buck switch on-time and

RT

2

I

switching frequency. Grounding this pin shuts down the controller.

Voltage Feedback from the regulated output - Input to the regulation and over-voltage comparators.

FB

3

I

The regulation level is 1.25V.

GND

4

-

Circuit Ground - Ground reference for all internal circuitry.

ISEN

5

I

sense. Connect to the PFET source and the sense resistor when using a current sense resistor.

PGATE

6

O

Gate Driver Output - Connect to the gate of the external PFET.

Output of the gate driver bias regulator - Output of the negative voltage regulator (relative to VIN) that

VCC

7

O

biases the PFET gate driver. A low ESR capacitor is required from VIN to VCC, located as close as

possible to the pins.

Input supply voltage - The operating input range is from 4.5V to 42V. A low ESR bypass capacitor

VIN

8

I

must be located as close as possible to the VIN and GND pins.

Exposed Pad - Exposed pad on the underside of the package (HVSSOP-PowerPAD-8 and WSON

EP

-

only). This pad is to be soldered to the PC board ground plane to aid in heat dissipation.

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