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SM59A16U1 Scheda tecnica(PDF) 1 Page - SyncMOS Technologies,Inc |
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SM59A16U1 Scheda tecnica(HTML) 1 Page - SyncMOS Technologies,Inc |
1 / 146 page SM59A16U1 8-Bit Micro-controller 64KB with ISP Flash & 6K+256B RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M071 Ver A SM59A16U1 04/12/2013 - 1 - Product List ................................................................................................................................................................. 6 Description .................................................................................................................................................................. 6 Ordering Information .................................................................................................................................................... 6 Features ...................................................................................................................................................................... 6 Pin Configuration ......................................................................................................................................................... 8 Block Diagram ............................................................................................................................................................. 9 Pin Description .......................................................................................................................................................... 10 Special Function Register ( SFR ) .............................................................................................................................. 13 Function Description .................................................................................................................................................. 22 1. General Features .......................................................................................................................................... 22 1.1 Embedded Flash................................................................................................................................... 22 1.2 IO Pads ................................................................................................................................................ 22 1.3 2T/1T Selection..................................................................................................................................... 22 1.4 RESET ................................................................................................................................................. 23 1.4.1 Hardware RESET Function........................................................................................................... 23 1.4.2 Software RESET Function ............................................................................................................ 23 1.4.3 Time Access Key Register( TAKEY ) ............................................................................................. 23 1.4.4 Software Reset Register( SWRES ) .............................................................................................. 23 1.4.5 Example Of Software Reset .......................................................................................................... 24 1.5 Clocks................................................................................................................................................... 24 2. Instruction Set ............................................................................................................................................... 25 3. Memory Structure.......................................................................................................................................... 29 3.1 Program Memory .................................................................................................................................. 29 3.2 Data Memory ........................................................................................................................................ 30 3.3 Data Memory - Lower 128 Byte( 00h to 7Fh ) ........................................................................................ 31 3.4 Data Memory - Higher 128 Byte( 80h to FFh ) ....................................................................................... 31 3.5 Data Memory - Expanded 6K Bytes( 0000h ~ 0x17FFh ) ....................................................................... 31 4. CPU Engine .................................................................................................................................................. 32 4.1 Accumulator.......................................................................................................................................... 33 4.2 B Register............................................................................................................................................. 33 4.3 Program Status Word ( PSW )............................................................................................................... 34 4.4 Stack Pointer ( SP )............................................................................................................................... 34 4.5 Data Pointer( DP )................................................................................................................................. 34 4.6 Data Pointer 1( DP1 )............................................................................................................................ 35 4.7 Auxiliary Register( AUX )....................................................................................................................... 35 4.8 Internal RAM Control Register( RCON ) ................................................................................................ 36 4.9 Clock Control Register( CKCON ) ......................................................................................................... 36 4.10 Interface Control Register( IFCON ) ...................................................................................................... 37 4.11 Page Select( PAGESEL ) ...................................................................................................................... 37 4.12 PWM Address Register( PWMADDR )................................................................................................... 38 4.13 PWM Data Register( PWMDATA ) ......................................................................................................... 38 4.14 USB Address Register( USBADDR ) ..................................................................................................... 39 4.15 USB Data Register( USBDATA )............................................................................................................ 39 5. GPIO............................................................................................................................................................. 40 5.1 P0 ( Port 0 Register ) ............................................................................................................................ 40 5.2 P1 ( Port 1 Register) ............................................................................................................................. 40 5.3 P2 ( Port 2 Register ) ............................................................................................................................ 41 5.4 P3 ( Port 3 Register ) ............................................................................................................................ 41 5.5 P4 ( Port 4 Register ) ............................................................................................................................ 41 6. Multiplication Division Unit( MDU )................................................................................................................. 42 6.1 Operating Registers of the MDU............................................................................................................ 42 6.2 Operation of the MDU ........................................................................................................................... 43 6.2.1 First phase: loading the MDx registers, x = 0~5:............................................................................ 43 6.2.2 Second phase: executing calculation. ........................................................................................... 43 6.2.3 Third phase: reading the result from the MDx registers.................................................................. 44 6.3 Normalizing........................................................................................................................................... 44 |
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