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ISL3179EFBZ Scheda tecnica(PDF) 7 Page - Intersil Corporation |
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ISL3179EFBZ Scheda tecnica(HTML) 7 Page - Intersil Corporation |
7 / 18 page ISL3179E, ISL3180E 7 FN6365.5 August 25, 2015 Submit Document Feedback Receiver Skew | tPLH - tPHL |tSKD Figure 8 Full - 0 1.5 ns Receiver Enable to Output High tZH RL = 1kΩ, CL = 15pF, SW = GND (Figure 9), (Note 11) Full - 10 15 ns Receiver Enable to Output Low tZL RL = 1kΩ, CL = 15pF, SW = VCC (Figure 9), (Note 11) Full - 11 15 ns Receiver Disable from Output High tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 9)Full - 10 15 ns Receiver Disable from Output Low tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 9)Full - 10 15 ns Time to Shutdown tSHDN (Note 12)Full 60 - 600 ns Receiver Enable from Shutdown to Output High tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 9), (Notes 12, 14) Full - - 1000 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 9), (Notes 12, 14) Full - - 1000 ns NOTES: 7. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 8. Supply current specification is valid for loaded drivers when DE = 0V. 9. Applies to peak current. See “Typical Performance Curves” on page 9 for more information. 10. Because of the shutdown feature, keep RE = 0 to prevent the device from entering SHDN. 11. Because of the shutdown feature, the RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN. 12. These IC’s are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 700ns, the parts are guaranteed to have entered shutdown. See “Low Power Shutdown Mode” on page 13. 13. Keep RE = VCC, and set the DE signal low time >700ns to ensure that the device enters SHDN. 14. Set the RE signal high time >700ns to ensure that the device enters SHDN. 15. This is the part-to-part skew between any two units tested with identical test conditions (Temperature, VCC, etc.). 16. VCC = 3.3V ±5% 17. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Electrical Specifications Test Conditions: VCC = 3.0V to 3.6V; Typicals are at VCC = 3.3V, TA = +25°C. Boldface limits apply across the operating temperature range. (Note 7) (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN (Note 17)TYP MAX (Note 17)UNIT Test Circuits and Waveforms FIGURE 4A. VOD AND VOC FIGURE 4B. VOD WITH COMMON-MODE LOAD FIGURE 4. DC DRIVER TEST CIRCUITS D DE DI VCC VOD VOC RL/2 RL/2 Z Y D DE DI VCC VOD 375Ω 375Ω Z Y RL = 60Ω VCM -7V TO +12V |
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