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AM3874 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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AM3874 Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 361 page AM3874, AM3871 www.ti.com SPRS695C – SEPTEMBER 2011 – REVISED DECEMBER 2013 SEE ADDITIONS/MODIFICATIONS/DELETIONS Table 7-27, Maximum Module Clock Frequencies: • Updated/Changed Media Controller CLOCK SOURCES from "PLL_MEDIACTL" to Section 7.4.10 "PLL_MEDIACTL/2" Module Clocks • Updated/Changed Media Controller MAX FREQUENCY OPP100 (MHz) value from "400" to "200" • Added footnote, "The maximum frequencies listed..." Section 8.4.1, EDMA Channel Synchronization Events: • Updated/Changed paragraphs Section 8.4 Section 8.4.2, EDMA Peripheral Register Descriptions: EDMA • Added Table 8-5, EDMA Channel Controller (EDMA TPCC) Control Registers • Added Table 8-6, EDMA Transfer Controller (EDMA TPTC) Control Registers Table 8-8, JTAG ID Register Table: Section 8.5.3 IEEE 1149.1 JTAG • Added silicon-revision specific information to the VARIANT bit field Section 8.6.2.3 EMAC RGMII Electrical • Updated/Changed all instances of "at DSP" to "at device" Data/Timing Table 8-42, Timing Requirements for HDVPSS Input: Section 8.10.1 HDVPSS Electrical • Deleted NO. 7, tt(CLK), Transition time, VIN[x]A_CLK (10%-90%) Data/Timing • Deleted NO. 7, tt(CLK), Transition time, VIN[x]B_CLK (10%-90%) Table 8-53, Switching Characteristics Over Recommended Operating Conditions for DDR2/DDR3 Section 8.13.4, Memory Controller: DDR2/DDR3 Memory • Updated/Changed NO. 1, tc(DDR_CLK) , Cycle time, DDR[x]_CLK, DDR2/DDR3 mode to DDR2 Controller Electrical mode Data/Timing • Added additional row to NO.1, tc(DDR_CLK), Cycle time, DDR[x]_CLK: DDR3 mode Section 8.13.4.1.1.1, DDR2 Interface Schematic: • Updated/Changed the sentence from, "... pins by pulling the non-inverted DQS pin..." to "... Section 8.13.4.1 DDR[x]_DQS[n] pins to the corresponding..." DDR2 Routing Specifications • Updated/Changed a sentence from, "... inverted DQS pin..." to "... DDR[x]_DQS[n] pins..." • Added sentence, "The DVDD_DDR[x] and VREFSSTL_DDR[x] power..." Section 8.13.4.1.2 Table 8-63, CK and ADDR_CTRL Routing Specification: DDR2 CK and • Updated/Changed the "Series terminator,...the DSP" footnote to "Series terminator,..the processor" ADDR_CTRL Routing Section 8.13.4.2.4, DDR3 Interface Schematic: • Combined 16-Bit and 32-Bit DDR3 Interface subsections Section 8.13.4.2 DDR3 Routing • Deleted repeated figure references Specifications • Deleted the sentence, "and the unused DQS......pulled to ground via 1-k Ω resistors." • Added sentence, "The DVDD_DDR[x] and VREFSSTL_DDR[x]..." Table 8-66, Compatible JEDEC DDR3 Devices (Per Interface): Section 8.13.4.2.4.1 Compatible JEDEC DDR3 • Updated/Changed the max clock rate in footnote, "DDR3 devices with speed...." from "400" MHz to Devices "533" MHz Table 8-78, Timing Requirements for McASP: Section 8.14.3 • Updated/Changed McASP1 Only ACLKR/X ext out, MIN value for NO. 5, tsu(AFSRX-ACLKRX), Setup McASP (McASP[5:0]) time, MCA[x]_AFSR/X input valid before MCA[X]_ACLKR/X from "4" to "2" ns. Electrical Data/Timing • Updated/Changed McASP1 Only ACLKR/X ext out, MIN value for NO. 7,tsu(AXR-ACLKRX), Setup time, MCA[x]_AXR input valid before MCA[X]_ACLKR/X from "4" to "2" ns. Table 8-80, McBSP Registers: Section 8.15 • Updated/Changed McBSP HEX ADDRESS range from "0x4700 0000 - 0x4700 00C0" to "0x4700 Multichannel Buffered 0100 – 0x4700 01C0" (DDR_REG to STATUS_REG) Serial Port (McBSP) • Added McBSP registers in HEX ADDRESS range "0x4700 0000 – 0x4700 004C" (REVNB to DMATXWAKE_EN) Section 9.1.2 • Updated/Changed "TI device nomenclature also includes ..." paragraph Device and Development- Support Tool Nomenclature Copyright © 2011–2013, Texas Instruments Incorporated Contents 9 Submit Documentation Feedback Product Folder Links: AM3874 AM3871 |
Codice articolo simile - AM3874_15 |
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