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AM3358-EP Scheda tecnica(PDF) 1 Page - Texas Instruments |
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AM3358-EP Scheda tecnica(HTML) 1 Page - Texas Instruments |
1 / 231 page Product Folder Sample & Buy Technical Documents Tools & Software Support & Community AM3358-EP SLUSC35A – APRIL 2015 – REVISED APRIL 2015 AM3358-EP Sitara™ Processors 1 Device Summary 1.1 Features 1 – Supports Protocols such as PROFIBUS, • Up to 800-MHz Sitara™ ARM® Cortex®-A8 32 ‑Bit PROFINET, EtherNet/IP™, and More RISC Processor – Two Programmable Real-Time Units (PRUs) – NEON™ SIMD Coprocessor • 32-Bit Load/Store RISC Processor Capable – 32KB of L1 Instruction and 32KB of Data Cache of Running at 200 MHz With Single-Error Detection (Parity) • 8KB of Instruction RAM With Single-Error – 256KB of L2 Cache With Error Correcting Code Detection (Parity) (ECC) • 8KB of Data RAM With Single-Error – 176KB of On-Chip Boot ROM Detection (Parity) – 64KB of Dedicated RAM • Single-Cycle 32-Bit Multiplier With 64-Bit – Emulation and Debug - JTAG Accumulator – Interrupt Controller (up to 128 Interrupt • Enhanced GPIO Module Provides Shift- Requests) In/Out Support and Parallel Latch on • On-Chip Memory (Shared L3 RAM) External Signal – 64KB of General-Purpose On-Chip Memory – 12KB of Shared RAM With Single-Error Controller (OCMC) RAM Detection (Parity) – Accessible to All Masters – Three 120-Byte Register Banks Accessible by – Supports Retention for Fast Wakeup Each PRU • External Memory Interfaces (EMIF) – Interrupt Controller Module (INTC) for Handling – mDDR(LPDDR), DDR2, DDR3, DDR3L System Input Events Controller: – Local Interconnect Bus for Connecting Internal • mDDR: 200-MHz Clock (400-MHz Data and External Masters to the Resources Inside Rate) the PRU-ICSS • DDR2: 266-MHz Clock (532-MHz Data Rate) – Peripherals Inside the PRU-ICSS: • DDR3: 400-MHz Clock (800-MHz Data Rate) • One UART Port With Flow Control Pins, • DDR3L: 400-MHz Clock (800-MHz Data Supports up to 12 Mbps Rate) • One Enhanced Capture (eCAP) Module • 16-Bit Data Bus • Two MII Ethernet Ports that Support • 1GB of Total Addressable Space Industrial Ethernet • Supports One x16 or Two x8 Memory Device • One MDIO Port Configurations • Power, Reset, and Clock Management (PRCM) – General-Purpose Memory Controller (GPMC) Module • Flexible 8-Bit and 16-Bit Asynchronous – Controls the Entry and Exit of Stand-By and Memory Interface With up to Seven Chip Deep-Sleep Modes Selects (NAND, NOR, Muxed-NOR, SRAM) – Responsible for Sleep Sequencing, Power • Uses BCH Code to Support 4-, 8-, or 16-Bit Domain Switch-Off Sequencing, Wake-Up ECC Sequencing, and Power Domain Switch-On Sequencing • Uses Hamming Code to Support 1-Bit ECC – Clocks – Error Locator Module (ELM) • Integrated 15- to 35-MHz High-Frequency • Used in Conjunction With the GPMC to Oscillator Used to Generate a Reference Locate Addresses of Data Errors from Clock for Various System and Peripheral Syndrome Polynomials Generated Using a Clocks BCH Algorithm • Supports Individual Clock Enable and • Supports 4-, 8-, and 16-Bit per 512-Byte Disable Control for Subsystems and Block Error Location Based on BCH Peripherals to Facilitate Reduced Power Algorithms Consumption • Programmable Real-Time Unit Subsystem and • Five ADPLLs to Generate System Clocks Industrial Communication Subsystem (PRU-ICSS) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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