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CSD43301Q5M Scheda tecnica(PDF) 8 Page - Texas Instruments

Il numero della parte CSD43301Q5M
Spiegazioni elettronici  NexFET??Smart Synchronous Rectifier
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CSD43301Q5M Scheda tecnica(HTML) 8 Page - Texas Instruments

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CSD43301Q5M
SLPS380B – DECEMBER 2012 – REVISED MAY 2013
www.ti.com
Recommended PCB Design Overview
The CSD43301Q5M features extremely low nominal RON. In order to maximize the performance of this device,
some simple layout guidelines should be followed.
The DRAIN pins of the CSD43301Q5M should be placed as close as possible to the inductor and connected
with a short wide trace. This reduces PCB conduction losses and reduce switching noise level. (1)
The GND pin (pin 7) must be connected into the thermal pad (pin 13) on the bottom of the device via a
copper pour (without thermal spokes) for maximum performance.
The CSD43301Q5M has the ability to use the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of
solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize
the amount of solder attach that will wick down via the barrel:
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in Figure 11 uses vias with a 10 mil drill
hole and a 16 mil capture pad.
Tent the opposite side of the via with a solder mask.
In the end, the number and size of the thermal vias should align with the end user's PCB design rules and
manufacturing types.
Figure 11. Recommended PCB Layout (Top Down View)
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
8
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Copyright © 2012–2013, Texas Instruments Incorporated


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