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OPT9221 Scheda tecnica(PDF) 4 Page - Texas Instruments |
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OPT9221 Scheda tecnica(HTML) 4 Page - Texas Instruments |
4 / 104 page OPT9221 SBAS703A – JUNE 2015 – REVISED JUNE 2015 www.ti.com Pin Functions (continued) PIN I/O I/O I/O BANK DESCRIPTION STANDARD NAME NO. CAP_BIT_CLKM M16 Input LVDS VCCIO5 Sensor data bit clk CAP_BIT_CLKP M15 Input LVDS VCCIO5 Sensor data bit clk CAP_DATA_DIFF_0M N16 Input LVDS VCCIO5 Sensor differential data ch 0 CAP_DATA_DIFF_0P N15 Input LVDS VCCIO5 Sensor differential data ch 0 CAP_DATA_DIFF_1M K16 Input LVDS VCCIO5 Sensor differential data ch 1 CAP_DATA_DIFF_1P K15 Input LVDS VCCIO5 Sensor differential data ch 1 CAP_DATA_SUM_M J16 Input LVDS VCCIO5 Sensor common mode data CAP_DATA_SUM_P J15 Input LVDS VCCIO5 Sensor common mode data CAP_FRM_CLKM P16 Input LVDS VCCIO5 Sensor sample clk CAP_FRM_CLKP R16 Input LVDS VCCIO5 Sensor sample clk Feedback signal from the external illumination modulation COMP_MOD_FB E16 Input 3.3 V VCCIO6 feedback comparator. Reference modulation signal for measuring external COMP_MOD_REF F16 Output 3.3 V VCCIO6 illumination modulation feedback comparator delay. SSTL-18 DDR2_ADDR_0 L11 Output VCCIO4 DDR address signal 0 Class I SSTL-18 DDR2_ADDR_1 L9 Output VCCIO4 DDR address signal 1 Class I SSTL-18 DDR2_ADDR_2 K10 Output VCCIO4 DDR address signal 2 Class I SSTL-18 DDR2_ADDR_3 K9 Output VCCIO4 DDR address signal 3 Class I SSTL-18 DDR2_ADDR_4 M11 Output VCCIO4 DDR address signal 4 Class I SSTL-18 DDR2_ADDR_5 M9 Output VCCIO4 DDR address signal 5 Class I SSTL-18 DDR2_ADDR_6 L10 Output VCCIO4 DDR address signal 6 Class I SSTL-18 DDR2_ADDR_7 T6 Output VCCIO3 DDR address signal 7 Class I SSTL-18 DDR2_ADDR_8 N11 Output VCCIO4 DDR address signal 8 Class I SSTL-18 DDR2_ADDR_9 P9 Output VCCIO4 DDR address signal 9 Class I SSTL-18 DDR2_ADDR_10 N3 Output VCCIO3 DDR address signal 10 Class I SSTL-18 DDR2_ADDR_11 M10 Output VCCIO4 DDR address signal 11 Class I SSTL-18 DDR2_ADDR_12 T5 Output VCCIO3 DDR address signal 12 Class I SSTL-18 DDR2_BA_0 R4 Output VCCIO3 DDR bank signal Class I SSTL-18 DDR2_BA_1 T4 Output VCCIO3 DDR bank signal Class I SSTL-18 DDR2_CASZ T11 Output VCCIO4 DDR CAS Class I SSTL-18 DDR2_CKE T2 Output VCCIO3 DDR clock enable Class I SSTL-18 DDR2_CLK_0 R14 Output VCCIO4 DDR clock Class I SSTL-18 DDR2_CLKz_0 P14 Output VCCIO4 DDR clock Class I 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: OPT9221 |
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