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AMC1100DWVR Scheda tecnica(PDF) 5 Page - Texas Instruments |
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AMC1100DWVR Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 33 page AMC1100 www.ti.com SBAS562A – APRIL 2012 – REVISED DECEMBER 2014 6.7 IEC Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. I/O circuitry failure can allow low resistance to either ground or supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, thus potentially leading to secondary system failures. The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determine the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IS Safety input, output, or supply current θJA = 246°C/W, VIN = 5.5 V, TJ = +150°C, TA = +25°C 10 mA TC Maximum-case temperature +150 °C 6.8 IEC 61000-4-5 Ratings PARAMETER TEST CONDITIONS VALUE UNIT VIOSM Surge immunity 1.2- μs or 50-μs voltage surge and 8-μs or 20-μs current surge ±6000 V 6.9 IEC 60664-1 Ratings PARAMETER TEST CONDITIONS SPECIFICATION Basic isolation group Material group II Rated mains voltage ≤ 150 VRMS I-IV Rated mains voltage ≤ 300 VRMS I-IV Installation classification Rated mains voltage ≤ 400 VRMS I-III Rated mains voltage < 600 VRMS I-III 6.10 Package Characteristics (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Shortest terminal-to-terminal distance L(I01) Minimum air gap (clearance) 7 mm through air Shortest terminal-to-terminal distance L(I02) Minimum external tracking (creepage) 7 mm across package surface Tracking resistance CTI DIN IEC 60112 and VDE 0303 part 1 > 400 V (comparative tracking index) Minimum internal gap Distance through insulation 0.014 mm (internal clearance) Input to output, VIO = 500 V, all pins on each side of the barrier tied together to > 1012 Ω create a two-terminal device, TA < +85°C RIO Isolation resistance Input to output, VIO = 500 V, > 1011 Ω +85°C ≤ TA < TA max CIO Barrier capacitance input to output VI = 0.5 VPP at 1 MHz 1.2 pF CI Input capacitance to ground VI = 0.5 VPP at 1 MHz 3 pF (1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of a specific application. Care should be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal according to the measurement techniques shown in the Isolation Glossary section. Techniques such as inserting grooves or ribs on the PCB are used to help increase these specifications. Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: AMC1100 |
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