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STC5420 Scheda tecnica(PDF) 8 Page - Connor-Winfield Corporation |
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STC5420 Scheda tecnica(HTML) 8 Page - Connor-Winfield Corporation |
8 / 70 page Page 8 of 70 Rev:2.0 Date: September 28, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5420 Synchronous Clock for SETS Data sheet A0/SDI 69 I A0~A6: Address pins for bus interface Intel and Motorola SDI: SPI bus data input CLKE: Clock edge selection for SPI A1/CLKE 68 I A2 67 I A3 66 I A4 65 I A5 64 I A6 63 I AD0/SDO 83 I/O AD0~AD7: Bus interface Intel and Motorola data pins Multiplex data and address pins SDO: SPI bus data output AD1 82 I/O AD2 81 I/O AD3 80 I/O AD4 79 I/O AD5 78 I/O AD6 77 I/O AD7 76 I/O NC 3, 4, 17, 22, 24, 25, 26, 27, 28, 29, 44, 96, 97, 98, 100 No connection. Pins are recommended to be tied to ground Table 1: Pin Description Pin Name Pin # I/O Description |
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