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74AXP2G07 Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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74AXP2G07 Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 74AXP2G07 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 1 — 24 September 2014 9 of 16 NXP Semiconductors 74AXP2G07 Low-power dual buffer with open-drain output Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 11. Test circuit for measuring switching times Table 10. Test data Supply voltage Load VEXT VCC CL RL tPZL, tPLZ 0.75 V to 2.7 V 5 pF 10 k 2VCC |
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