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74AUP3G04 Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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74AUP3G04 Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 22 page 74AUP3G04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 — 29 January 2013 3 of 22 NXP Semiconductors 74AUP3G04 Low-power triple inverter 5. Functional diagram 6. Pinning information 6.1 Pinning Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 001aah793 1A 1Y 2A 2Y 3A 3Y 1 1 001aah794 1 mna110 A Y Fig 4. Pin configuration SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089, SOT1116 and SOT1203 74AUP3G04 1A VCC 3Y 1Y 2A 3A GND 2Y 001aag450 1 2 3 4 6 5 8 7 74AUP3G04 3A 1Y VCC 2Y 2A 3Y 1A GND 001aag451 36 27 18 45 Transparent top view |
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