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74AUP1G07 Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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74AUP1G07 Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 19 page 74AUP1G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 — 16 July 2012 9 of 19 NXP Semiconductors 74AUP1G07 Low-power buffer with open-drain output 12. Waveforms [1] For measuring enable and disable times, RL = 5 k, for measuring propagation delays, setup and hold times and pulse width, RL = 1 M . Measurement points are given in Table 9. Logic level: VOL is the typical output voltage level that occurs with the output load. Fig 8. The data input (A) to output (Y) propagation delays mna626 tPLZ VX Y output A input VI VCC VM VOL GND tPZL VM Table 9. Measurement points Supply voltage Input Output VCC VM VM VX 0.8 V to 1.6 V 0.5 V CC 0.5 V CC VOL +0.1 V 1.65 V to 2.7 V 0.5 V CC 0.5 V CC VOL +0.15V 3.0 V to 3.6 V 0.5 V CC 0.5 V CC VOL +0.3 V Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 9. Load circuitry for switching times 001aac521 DUT RT VI VO VEXT VCC RL 5 k Ω CL G Table 10. Test data Supply voltage Load VEXT VCC CL RL[1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2 V CC |
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