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74AUP1G04 Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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74AUP1G04 Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 22 page 74AUP1G04 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 7 — 27 June 2012 10 of 22 NXP Semiconductors 74AUP1G04 Low-power inverter [1] tpd is the same as tPLH and tPHL. 12. Waveforms CL = 15 pF tpd propagation delay A to Y; see Figure 8 [1] VCC = 1.1 V to 1.3 V 3.0 15.8 3.0 17.4 ns VCC = 1.4 V to 1.6 V 2.4 10.0 2.4 11.0 ns VCC = 1.65 V to 1.95 V 2.1 8.0 2.1 8.8 ns VCC = 2.3 V to 2.7 V 1.8 6.1 1.8 6.8 ns VCC = 3.0 V to 3.6 V 1.8 5.0 1.8 5.5 ns CL = 30 pF tpd propagation delay A to Y; see Figure 8 [1] VCC = 1.1 V to 1.3 V 4.0 19.0 4.0 20.9 ns VCC = 1.4 V to 1.6 V 3.2 12.9 3.2 14.2 ns VCC = 1.65 V to 1.95 V 2.9 10.5 2.9 11.6 ns VCC = 2.3 V to 2.7 V 2.6 7.6 2.6 8.4 ns VCC = 3.0 V to 3.6 V 2.6 6.2 2.6 6.9 ns Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9 Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 8. The data input (A) to output (Y) propagation delays mna640 tPHL tPLH VM VM A input Y output GND VI VOH VOL Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns |
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