Motore di ricerca datesheet componenti elettronici |
|
AM3517 Scheda tecnica(PDF) 2 Page - Texas Instruments |
|
AM3517 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 222 page AM3517, AM3505 SPRS550D – OCTOBER 2009 – REVISED MARCH 2012 www.ti.com – Built-in Digital Clamping and Black Level 1.1 and 2.0, OpenVG1.0 Compensation – Fine Grained Task Switching, Load – 10-bit to 8-bit A-law Compression Hardware Balancing, and Power Management – Supports up to 16K Pixels (Image Size) in – Programmable, High-Quality Image Anti- Horizontal and Vertical Directions Aliasing • System Direct Memory Access (sDMA) • Endianess Controller (32 Logical Channels With – ARM Instructions - Little Endian Configurable Priority) – ARM Data – Configurable • Comprehensive Power, Reset and Clock • SDRC Memory Controller Management – 16/32-bit Memory Controller With 1G-Byte • ARM Cortex™-A8 Memory Architecture Total Address Space – ARMv7 Architecture – Double Data Rate (DDR2) SDRAM, mobile – In-Order, Dual-Issue, Superscalar Double Data Rate (mDDR)SDRAM Microprocessor Core – SDRAM Memory Scheduler (SMS) and – ARM NEON™ Multimedia Architecture Rotation Engine – Over 2x Performance of ARMv6 SIMD • General Purpose Memory Controller (GPMC) – Supports Both Integer and Floating Point – 16-bit Wide Multiplexed Address/Data Bus SIMD – Up to 8 Chip Select Pins With 128M-Byte – Jazelle® RCT Execution Environment Address Space per Chip Select Pin Architecture – Glueless Interface to NOR Flash, NAND – Dynamic Branch Prediction with Branch Flash (With ECC Hamming Code Target Address Cache, Global history buffer Calculation), SRAM and Pseudo-SRAM and 8 entry return stack – Flexible Asynchronous Protocol Control for – Embedded Trace Macrocell [ETM] support Interface to Custom Logic (FPGA, CPLD, for Non_invasive Debug ASICs, etc.) – 16K-Byte instruction Cache (4-Way set- – Nonmultiplexed Address/Data Mode (Limited associative) 2K-Byte Address Space) – 16K-Byte Data Cache (4-Way Set- • Test Interfaces Associative) – IEEE-1149.1 (JTAG) Boundary-Scan – 256K-Byte L2 Cache Compatible • PowerVR SGX™ Graphics Accelerator (AM3517 – Embedded Trace Macro Interface (ETM) only) • 65-nm CMOS technology – Tile Based Architecture Delivering up to 10 • Packages: MPoly/sec – 491-pin BGA (17x17, 0.65mm pitch) – Universal Scalable Shader Engine: Multi- [ZCN suffix] threaded Engine Incorporating Pixel and with via channel array technology Vertex Shader Functionality – 484-pin PBGA (23x23, 1-mm pitch) – Industry Standard API Support: OpenGLES [ZER suffix] 1.2 Applications • Single Board Computers • Transportation • Industrial and Home Automation • Navigation • Digital Signage • Smart White Goods • Point of Service • Digital TV • Portable Media Player • Digital Video Camera • Portable Industrial • Gaming 2 Device Summary Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3517 AM3505 |
Codice articolo simile - AM3517_12 |
|
Descrizione simile - AM3517_12 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEETIT.COM |
Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |