3-8

Detailed Description

Theory of Operation

The ISL5640 is a dual 8-bit fully differential sampling pipeline

A/D converter with digital error correction logic. Figure 15

depicts the circuit for the front end differential-in-differential-

out sample-and-hold (S/H) amplifiers. The switches are

controlled by an internal sampling clock which is a non-

overlapping two phase signal

master sampling clock. During the sampling phase,

analog ground. At the falling edge of

sampled on the bottom plates of the sampling capacitors. In

the next clock phase,

sampling capacitors are connected together and the holding

capacitors are switched to the op amp output nodes. The

sample-and-hold cycle. The front end sample-and-hold output

is a fully-differential, sampled-data representation of the

analog input. The circuit not only performs the sample-and-

hold function but will also convert a single-ended input to a

fully-differential output for the converter core. During the

components result in a typical full power input bandwidth of

400MHz for the converter.

As illustrated in the Functional Block Diagram and the timing

diagram in Figure 1, eight identical pipeline subconverter

stages, each containing a two-bit flash converter and a two-

bit multiplying digital-to-analog converter, follow the S/H

circuit with the ninth stage being a two bit flash converter.

Each converter stage in the pipeline will be sampling in one

phase and amplifying in the other clock phase. Each

individual subconverter clock signal is offset by 180 degrees

from the previous stage clock signal resulting in alternate

stages in the pipeline performing the same operation.

The output of each of the eight identical two-bit subconverter

stages is a two-bit digital word containing a supplementary bit

to be used by the digital error correction logic. The output of

each subconverter stage is input to a digital delay line which is

controlled by the internal sampling clock. The function of the

digital delay line is to time align the digital outputs of the eight

identical two-bit subconverter stages with the corresponding

output of the ninth stage flash converter before applying the

eighteen bit result to the digital error correction logic. The

digital error correction logic uses the supplementary bits to

correct any error that may exist before generating the final ten

bit digital data output of the converter.

Because of the pipeline nature of this converter, the digital

data representing an analog input sample is output to the

digital data bus following the 6th cycle of the clock after the

TABLE 1. A/D CODE TABLE

CODE CENTER

DESCRIPTION

DIFFERENTIAL INPUT

VOLTAGE

OFFSET BINARY OUTPUT CODE

MSB

LSB

I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0

0.499756V

1

1

11111111

0.498779V

1

1

11111110

732.422

µV

1

000000000

-244.141

µV

0

111111111

-0.498291V

0

0

00000001

-0.499268V

0

0

00000000

NOTE:

-

+

+

-

FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD

ISL5640